Lines Matching refs:isPPC64
152 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering() local
153 setMinStackArgumentAlignment(isPPC64 ? Align(8) : Align(4)); in PPCTargetLowering()
235 if (isPPC64 || Subtarget.hasFPCVT()) { in PPCTargetLowering()
238 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
241 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
245 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
248 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
252 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
255 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
259 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
262 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
430 if (Subtarget.hasP9Vector() && Subtarget.isPPC64()) in PPCTargetLowering()
510 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
651 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) { in PPCTargetLowering()
952 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
1244 setOperationAction(ISD::SELECT_CC, MVT::i64, isPPC64 ? Custom : Expand); in PPCTargetLowering()
1282 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom); in PPCTargetLowering()
1284 if (!isPPC64) { in PPCTargetLowering()
1299 if (!isPPC64) { in PPCTargetLowering()
1306 if (!isPPC64) in PPCTargetLowering()
1309 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1); in PPCTargetLowering()
1557 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4); in getByValTypeAlignment()
2749 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegImm()
2856 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegRegOnly()
3060 const bool Is64Bit = Subtarget.isPPC64(); in getTOCEntry()
3124 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) in isJumpTableRelative()
3131 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBase()
3148 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBaseExpr()
3283 bool is64bit = Subtarget.isPPC64(); in LowerGlobalTLSAddressLinux()
3532 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); in LowerVAARG()
3623 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"); in LowerVACOPY()
3704 bool isPPC64 = (PtrVT == MVT::i64); in LowerINIT_TRAMPOLINE() local
3714 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl, in LowerINIT_TRAMPOLINE()
3715 isPPC64 ? MVT::i64 : MVT::i32); in LowerINIT_TRAMPOLINE()
3738 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) { in LowerVASTART()
4960 bool isPPC64 = Subtarget.isPPC64(); in EmitTailCallStoreFPAndRetAddr() local
4961 int SlotSize = isPPC64 ? 8 : 4; in EmitTailCallStoreFPAndRetAddr()
4965 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in EmitTailCallStoreFPAndRetAddr()
4976 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, in CalculateTailCallArgDest() argument
4982 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in CalculateTailCallArgDest()
4999 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in EmitTailCallLoadFPAndRetAddr()
5026 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, in LowerMemOpCallTo() argument
5033 if (isPPC64) in LowerMemOpCallTo()
5043 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, in LowerMemOpCallTo()
5372 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall()
5373 const unsigned Alignment = Subtarget.isPPC64() ? 8 : 4; in prepareDescriptorIndirectCall()
5422 const bool IsPPC64 = Subtarget.isPPC64(); in buildCallOperands()
5587 else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) in LowerCall()
5638 if (Subtarget.isPPC64()) in LowerCall()
6527 const bool IsPPC64 = Subtarget.isPPC64(); in CC_AIX()
6870 const bool IsPPC64 = Subtarget.isPPC64(); in LowerFormalArguments_AIX()
7186 const bool IsPPC64 = Subtarget.isPPC64(); in LowerCall_AIX()
7450 const MVT PtrVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in LowerCall_AIX()
7581 bool isPPC64 = Subtarget.isPPC64(); in LowerSTACKRESTORE() local
7582 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; in LowerSTACKRESTORE()
7602 bool isPPC64 = Subtarget.isPPC64(); in getReturnAddrFrameIndex() local
7615 RASI = MF.getFrameInfo().CreateFixedObject(isPPC64? 8 : 4, LROffset, false); in getReturnAddrFrameIndex()
7625 bool isPPC64 = Subtarget.isPPC64(); in getFramePointerFrameIndex() local
7638 FPSI = MF.getFrameInfo().CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); in getFramePointerFrameIndex()
7671 bool isPPC64 = Subtarget.isPPC64(); in LowerEH_DWARF_CFA() local
7674 int FI = MF.getFrameInfo().CreateFixedObject(isPPC64 ? 8 : 4, 0, false); in LowerEH_DWARF_CFA()
8182 if (Subtarget.hasDirectMove() && Subtarget.isPPC64()) in LowerFP_TO_INT()
8473 Subtarget.isPPC64() && Subtarget.hasFPCVT()) in LowerINT_TO_FP()
8654 assert(Subtarget.isPPC64() && in LowerINT_TO_FP()
9174 if (Subtarget.hasVSX() && Subtarget.isPPC64() && in LowerBUILD_VECTOR()
10348 if (Subtarget.isPPC64()) in LowerINTRINSIC_WO_CHAIN()
10445 assert(Subtarget.isPPC64() && "Only 64-bit is supported for now."); in LowerINTRINSIC_VOID()
10461 if (!Subtarget.isPPC64()) in LowerBSWAP()
10546 if ((VT == MVT::v2i64 || VT == MVT::v2f64) && !Subtarget.isPPC64()) in LowerINSERT_VECTOR_ELT()
10941 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64()) in ReplaceNodeResults()
11016 if (isa<LoadInst>(Inst) && Subtarget.isPPC64()) in emitTrailingFence()
11233 bool is64bit = Subtarget.isPPC64(); in EmitPartwordAtomicBinary()
11501 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1; in emitEHSjLjSetJmp()
11503 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP; in emitEHSjLjSetJmp()
11506 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW)) in emitEHSjLjSetJmp()
11529 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg); in emitEHSjLjSetJmp()
11532 if (Subtarget.isPPC64()) { in emitEHSjLjSetJmp()
11695 const bool isPPC64 = Subtarget.isPPC64(); in emitProbedAlloca() local
11736 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1; in emitProbedAlloca()
11737 Register FinalStackPtr = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
11738 Register FramePointer = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
11739 Register ActualNegSizeReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
11747 isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_64 : PPC::PREPARE_PROBED_ALLOCA_32; in emitProbedAlloca()
11753 ProbeOpc = isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 in emitProbedAlloca()
11762 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::ADD8 : PPC::ADD4), in emitProbedAlloca()
11770 Register ScratchReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
11772 Register TempReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
11773 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS), TempReg) in emitProbedAlloca()
11775 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::ORI8 : PPC::ORI), in emitProbedAlloca()
11780 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LI8 : PPC::LI), ScratchReg) in emitProbedAlloca()
11785 Register Div = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
11786 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::DIVD : PPC::DIVW), Div) in emitProbedAlloca()
11789 Register Mul = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
11790 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::MULLD : PPC::MULLW), Mul) in emitProbedAlloca()
11793 Register NegMod = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
11794 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::SUBF8 : PPC::SUBF), NegMod) in emitProbedAlloca()
11797 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg) in emitProbedAlloca()
11806 BuildMI(TestMBB, DL, TII->get(isPPC64 ? PPC::CMPD : PPC::CMPW), CmpResult) in emitProbedAlloca()
11820 BuildMI(BlockMBB, DL, TII->get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg) in emitProbedAlloca()
11831 MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
11833 TII->get(isPPC64 ? PPC::DYNAREAOFFSET8 : PPC::DYNAREAOFFSET), in emitProbedAlloca()
11837 BuildMI(TailMBB, DL, TII->get(isPPC64 ? PPC::ADD8 : PPC::ADD4), DstReg) in emitProbedAlloca()
12238 bool is64bit = Subtarget.isPPC64(); in EmitInstrWithCustomInserter()
13350 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64()))) in DAGCombineExtBoolTrunc()
14804 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && Op1VT == MVT::i64))) { in PerformDAGCombine()
14839 if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() && in PerformDAGCombine()
15235 Subtarget.isPPC64() && N->getValueType(0) == MVT::i64; in PerformDAGCombine()
15482 if (VT == MVT::i64 && !Subtarget.isPPC64()) in BuildSDIVPow2()
15701 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
15705 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
15798 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() && in getRegForInlineAsmConstraint()
15959 bool isPPC64 = Subtarget.isPPC64(); in LowerRETURNADDR() local
15966 isPPC64 ? MVT::i64 : MVT::i32); in LowerRETURNADDR()
15988 bool isPPC64 = PtrVT == MVT::i64; in LowerFRAMEADDR() local
15994 FrameReg = isPPC64 ? PPC::X1 : PPC::R1; in LowerFRAMEADDR()
15996 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP; in LowerFRAMEADDR()
16010 bool isPPC64 = Subtarget.isPPC64(); in getRegisterByName() local
16012 bool is64Bit = isPPC64 && VT == LLT::scalar(64); in getRegisterByName()
16018 .Case("r2", isPPC64 ? Register() : PPC::R2) in getRegisterByName()
16180 if (Subtarget.isPPC64()) { in getOptimalMemOpType()
16219 (Subtarget.isPPC64() && MemVT == MVT::i32)) && in isZExtFree()
16401 return Subtarget.isPPC64() ? PPC::X3 : PPC::R3; in getExceptionPointerRegister()
16406 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4; in getExceptionSelectorRegister()
16600 if (!Subtarget.isISA3_0() || !Subtarget.isPPC64() || in combineSHL()
16644 if (!Subtarget.isPPC64()) in combineADDToADDZE()
17361 Disp = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectForceXFormMode()
17444 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectOptimalAddrMode()
17476 Disp = FI ? DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectOptimalAddrMode()