Lines Matching refs:RegVT
5372 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall() local
5376 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI, in prepareDescriptorIndirectCall()
5382 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff); in prepareDescriptorIndirectCall()
5384 DAG.getLoad(RegVT, dl, LDChain, AddTOC, in prepareDescriptorIndirectCall()
5389 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff); in prepareDescriptorIndirectCall()
5391 DAG.getLoad(RegVT, dl, LDChain, AddPtr, in prepareDescriptorIndirectCall()
5424 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in buildCallOperands() local
5447 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT); in buildCallOperands()
5450 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, StackPtr, TOCOff); in buildCallOperands()
5457 RegVT)); in buildCallOperands()
5462 Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT)); in buildCallOperands()
5480 Ops.push_back(DAG.getRegister(Subtarget.getTOCPointerRegister(), RegVT)); in buildCallOperands()
6529 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in CC_AIX() local
6560 State.getNextStackOffset(), RegVT, in CC_AIX()
6570 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, RegVT, LocInfo)); in CC_AIX()
6593 if (ValVT.getFixedSizeInBits() < RegVT.getFixedSizeInBits()) in CC_AIX()
6597 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, RegVT, LocInfo)); in CC_AIX()
6599 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, RegVT, LocInfo)); in CC_AIX()
6625 CCValAssign::getCustomReg(ValNo, ValVT, Reg, RegVT, LocInfo)); in CC_AIX()
6724 CCValAssign::getCustomReg(ValNo, ValVT, FirstReg, RegVT, LocInfo)); in CC_AIX()
6726 CCValAssign::getCustomReg(ValNo, ValVT, SecondReg, RegVT, LocInfo)); in CC_AIX()
6740 CCValAssign::getCustomReg(ValNo, ValVT, Reg, RegVT, LocInfo)); in CC_AIX()