Lines Matching refs:PPC
156 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
159 addRegisterClass(MVT::f32, &PPC::GPRCRegClass); in PPCTargetLowering()
162 addRegisterClass(MVT::f64, &PPC::SPERCRegClass); in PPCTargetLowering()
164 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
165 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
284 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass); in PPCTargetLowering()
691 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); in PPCTargetLowering()
888 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); in PPCTargetLowering()
889 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); in PPCTargetLowering()
890 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); in PPCTargetLowering()
891 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); in PPCTargetLowering()
1004 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass); in PPCTargetLowering()
1006 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass); in PPCTargetLowering()
1008 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass); in PPCTargetLowering()
1009 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass); in PPCTargetLowering()
1010 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass); in PPCTargetLowering()
1121 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass); in PPCTargetLowering()
1122 addRegisterClass(MVT::f128, &PPC::VRRCRegClass); in PPCTargetLowering()
1142 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass); in PPCTargetLowering()
1143 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass); in PPCTargetLowering()
1265 addRegisterClass(MVT::v256i1, &PPC::VSRpRCRegClass); in PPCTargetLowering()
1270 addRegisterClass(MVT::v512i1, &PPC::UACCRCRegClass); in PPCTargetLowering()
1309 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1); in PPCTargetLowering()
1386 case PPC::DIR_970: in PPCTargetLowering()
1387 case PPC::DIR_A2: in PPCTargetLowering()
1388 case PPC::DIR_E500: in PPCTargetLowering()
1389 case PPC::DIR_E500mc: in PPCTargetLowering()
1390 case PPC::DIR_E5500: in PPCTargetLowering()
1391 case PPC::DIR_PWR4: in PPCTargetLowering()
1392 case PPC::DIR_PWR5: in PPCTargetLowering()
1393 case PPC::DIR_PWR5X: in PPCTargetLowering()
1394 case PPC::DIR_PWR6: in PPCTargetLowering()
1395 case PPC::DIR_PWR6X: in PPCTargetLowering()
1396 case PPC::DIR_PWR7: in PPCTargetLowering()
1397 case PPC::DIR_PWR8: in PPCTargetLowering()
1398 case PPC::DIR_PWR9: in PPCTargetLowering()
1399 case PPC::DIR_PWR10: in PPCTargetLowering()
1400 case PPC::DIR_PWR_FUTURE: in PPCTargetLowering()
1415 if (Subtarget.getCPUDirective() == PPC::DIR_E500mc || in PPCTargetLowering()
1416 Subtarget.getCPUDirective() == PPC::DIR_E5500) { in PPCTargetLowering()
1423 } else if (Subtarget.getCPUDirective() == PPC::DIR_A2) { in PPCTargetLowering()
1475 AddrModesMap[PPC::AM_DForm] = { in initializeAddrModeMap()
1477 PPC::MOF_ZExt | PPC::MOF_RPlusSImm16 | PPC::MOF_WordInt, in initializeAddrModeMap()
1478 PPC::MOF_ZExt | PPC::MOF_RPlusLo | PPC::MOF_WordInt, in initializeAddrModeMap()
1479 PPC::MOF_ZExt | PPC::MOF_NotAddNorCst | PPC::MOF_WordInt, in initializeAddrModeMap()
1480 PPC::MOF_ZExt | PPC::MOF_AddrIsSImm32 | PPC::MOF_WordInt, in initializeAddrModeMap()
1482 PPC::MOF_ZExt | PPC::MOF_RPlusSImm16 | PPC::MOF_SubWordInt, in initializeAddrModeMap()
1483 PPC::MOF_ZExt | PPC::MOF_RPlusLo | PPC::MOF_SubWordInt, in initializeAddrModeMap()
1484 PPC::MOF_ZExt | PPC::MOF_NotAddNorCst | PPC::MOF_SubWordInt, in initializeAddrModeMap()
1485 PPC::MOF_ZExt | PPC::MOF_AddrIsSImm32 | PPC::MOF_SubWordInt, in initializeAddrModeMap()
1487 PPC::MOF_SExt | PPC::MOF_RPlusSImm16 | PPC::MOF_SubWordInt, in initializeAddrModeMap()
1488 PPC::MOF_SExt | PPC::MOF_RPlusLo | PPC::MOF_SubWordInt, in initializeAddrModeMap()
1489 PPC::MOF_SExt | PPC::MOF_NotAddNorCst | PPC::MOF_SubWordInt, in initializeAddrModeMap()
1490 PPC::MOF_SExt | PPC::MOF_AddrIsSImm32 | PPC::MOF_SubWordInt, in initializeAddrModeMap()
1492 PPC::MOF_RPlusSImm16 | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetBeforeP9, in initializeAddrModeMap()
1493 PPC::MOF_RPlusLo | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetBeforeP9, in initializeAddrModeMap()
1494 PPC::MOF_NotAddNorCst | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetBeforeP9, in initializeAddrModeMap()
1495 PPC::MOF_AddrIsSImm32 | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetBeforeP9, in initializeAddrModeMap()
1497 AddrModesMap[PPC::AM_DSForm] = { in initializeAddrModeMap()
1499 PPC::MOF_SExt | PPC::MOF_RPlusSImm16Mult4 | PPC::MOF_WordInt, in initializeAddrModeMap()
1500 PPC::MOF_SExt | PPC::MOF_NotAddNorCst | PPC::MOF_WordInt, in initializeAddrModeMap()
1501 PPC::MOF_SExt | PPC::MOF_AddrIsSImm32 | PPC::MOF_WordInt, in initializeAddrModeMap()
1503 PPC::MOF_RPlusSImm16Mult4 | PPC::MOF_DoubleWordInt, in initializeAddrModeMap()
1504 PPC::MOF_NotAddNorCst | PPC::MOF_DoubleWordInt, in initializeAddrModeMap()
1505 PPC::MOF_AddrIsSImm32 | PPC::MOF_DoubleWordInt, in initializeAddrModeMap()
1507 PPC::MOF_RPlusSImm16Mult4 | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetP9, in initializeAddrModeMap()
1508 PPC::MOF_NotAddNorCst | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetP9, in initializeAddrModeMap()
1509 PPC::MOF_AddrIsSImm32 | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetP9, in initializeAddrModeMap()
1511 AddrModesMap[PPC::AM_DQForm] = { in initializeAddrModeMap()
1513 PPC::MOF_RPlusSImm16Mult16 | PPC::MOF_Vector | PPC::MOF_SubtargetP9, in initializeAddrModeMap()
1514 PPC::MOF_NotAddNorCst | PPC::MOF_Vector | PPC::MOF_SubtargetP9, in initializeAddrModeMap()
1515 PPC::MOF_AddrIsSImm32 | PPC::MOF_Vector | PPC::MOF_SubtargetP9, in initializeAddrModeMap()
1516 PPC::MOF_RPlusSImm16Mult16 | PPC::MOF_Vector256 | PPC::MOF_SubtargetP10, in initializeAddrModeMap()
1517 PPC::MOF_NotAddNorCst | PPC::MOF_Vector256 | PPC::MOF_SubtargetP10, in initializeAddrModeMap()
1518 PPC::MOF_AddrIsSImm32 | PPC::MOF_Vector256 | PPC::MOF_SubtargetP10, in initializeAddrModeMap()
1776 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, in isVPKUHUMShuffleMask()
1807 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, in isVPKUWUMShuffleMask()
1844 bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, in isVPKUDUMShuffleMask()
1912 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, in isVMRGLShuffleMask()
1937 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, in isVMRGHShuffleMask()
2027 bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, in isVMRGEOShuffleMask()
2056 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, in isVSLDOIShuffleMask()
2100 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { in isSplatShuffleMask()
2168 bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, in isXXINSERTWMask()
2243 bool PPC::isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, in isXXSLDWIShuffleMask()
2318 bool PPC::isXXBRHShuffleMask(ShuffleVectorSDNode *N) { in isXXBRHShuffleMask()
2322 bool PPC::isXXBRWShuffleMask(ShuffleVectorSDNode *N) { in isXXBRWShuffleMask()
2326 bool PPC::isXXBRDShuffleMask(ShuffleVectorSDNode *N) { in isXXBRDShuffleMask()
2330 bool PPC::isXXBRQShuffleMask(ShuffleVectorSDNode *N) { in isXXBRQShuffleMask()
2342 bool PPC::isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &DM, in isXXPERMDIShuffleMask()
2398 unsigned PPC::getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, in getSplatIdxForPPCMnemonics()
2412 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { in get_VSPLTI_elt()
2749 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegImm()
2766 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; in SelectAddressRegImm()
2823 Base = DAG.getRegister(PPC::ZERO8, N.getValueType()); in SelectAddressRegImm34()
2856 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegRegOnly()
3062 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) in getTOCEntry()
3064 ? DAG.getRegister(PPC::R2, VT) in getTOCEntry()
3292 SDValue TLSReg = DAG.getRegister(PPC::X13, MVT::i64); in LowerGlobalTLSAddressLinux()
3304 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64) in LowerGlobalTLSAddressLinux()
3305 : DAG.getRegister(PPC::R2, MVT::i32); in LowerGlobalTLSAddressLinux()
3327 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddressLinux()
3354 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddressLinux()
3380 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddressLinux()
3679 if (Reg != PPC::LR && Reg != PPC::LR8) in LowerINLINEASM()
3817 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
3818 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
3819 PPC::F11, PPC::F12, PPC::F13};
4020 RC = &PPC::GPRCRegClass; in LowerFormalArguments_32SVR4()
4024 RC = &PPC::VSSRCRegClass; in LowerFormalArguments_32SVR4()
4026 RC = &PPC::GPRCRegClass; in LowerFormalArguments_32SVR4()
4028 RC = &PPC::F4RCRegClass; in LowerFormalArguments_32SVR4()
4032 RC = &PPC::VSFRCRegClass; in LowerFormalArguments_32SVR4()
4035 RC = &PPC::GPRCRegClass; in LowerFormalArguments_32SVR4()
4037 RC = &PPC::F8RCRegClass; in LowerFormalArguments_32SVR4()
4042 RC = &PPC::VRRCRegClass; in LowerFormalArguments_32SVR4()
4045 RC = &PPC::VRRCRegClass; in LowerFormalArguments_32SVR4()
4049 RC = &PPC::VRRCRegClass; in LowerFormalArguments_32SVR4()
4125 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in LowerFormalArguments_32SVR4()
4126 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in LowerFormalArguments_32SVR4()
4131 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, in LowerFormalArguments_32SVR4()
4132 PPC::F8 in LowerFormalArguments_32SVR4()
4161 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); in LowerFormalArguments_32SVR4()
4180 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); in LowerFormalArguments_32SVR4()
4238 PPC::X3, PPC::X4, PPC::X5, PPC::X6, in LowerFormalArguments_64SVR4()
4239 PPC::X7, PPC::X8, PPC::X9, PPC::X10, in LowerFormalArguments_64SVR4()
4242 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, in LowerFormalArguments_64SVR4()
4243 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerFormalArguments_64SVR4()
4364 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4()
4399 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4()
4423 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4()
4436 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4()
4466 ? &PPC::VSSRCRegClass in LowerFormalArguments_64SVR4()
4467 : &PPC::F4RCRegClass); in LowerFormalArguments_64SVR4()
4470 ? &PPC::VSFRCRegClass in LowerFormalArguments_64SVR4()
4471 : &PPC::F8RCRegClass); in LowerFormalArguments_64SVR4()
4482 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4()
4523 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); in LowerFormalArguments_64SVR4()
4582 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4()
4706 PPC::X3, PPC::X4, PPC::X5, PPC::X6, in needStackSlotPassParameters()
4707 PPC::X7, PPC::X8, PPC::X9, PPC::X10, in needStackSlotPassParameters()
4710 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, in needStackSlotPassParameters()
4711 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in needStackSlotPassParameters()
5034 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); in LowerMemOpCallTo()
5036 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); in LowerMemOpCallTo()
5462 Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT)); in buildCallOperands()
5484 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32)); in buildCallOperands()
5531 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || in FinishCall()
5754 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); in LowerCall_32SVR4()
5940 PPC::X3, PPC::X4, PPC::X5, PPC::X6, in LowerCall_64SVR4()
5941 PPC::X7, PPC::X8, PPC::X9, PPC::X10, in LowerCall_64SVR4()
5944 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, in LowerCall_64SVR4()
5945 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 in LowerCall_64SVR4()
6082 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64); in LowerCall_64SVR4()
6253 RegsToPass.push_back(std::make_pair(PPC::X11, Arg)); in LowerCall_64SVR4()
6455 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); in LowerCall_64SVR4()
6468 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee)); in LowerCall_64SVR4()
6496 case PPC::R5: in isGPRShadowAligned()
6497 case PPC::R9: in isGPRShadowAligned()
6498 case PPC::X3: in isGPRShadowAligned()
6499 case PPC::X5: in isGPRShadowAligned()
6500 case PPC::X7: in isGPRShadowAligned()
6501 case PPC::X9: in isGPRShadowAligned()
6505 case PPC::R3: in isGPRShadowAligned()
6506 case PPC::R7: in isGPRShadowAligned()
6507 case PPC::X4: in isGPRShadowAligned()
6508 case PPC::X6: in isGPRShadowAligned()
6509 case PPC::X8: in isGPRShadowAligned()
6510 case PPC::X10: in isGPRShadowAligned()
6513 case PPC::R4: in isGPRShadowAligned()
6514 case PPC::R6: in isGPRShadowAligned()
6515 case PPC::R8: in isGPRShadowAligned()
6516 case PPC::R10: in isGPRShadowAligned()
6538 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_AIX()
6539 PPC::R7, PPC::R8, PPC::R9, PPC::R10}; in CC_AIX()
6541 PPC::X3, PPC::X4, PPC::X5, PPC::X6, in CC_AIX()
6542 PPC::X7, PPC::X8, PPC::X9, PPC::X10}; in CC_AIX()
6545 PPC::V2, PPC::V3, PPC::V4, PPC::V5, in CC_AIX()
6546 PPC::V6, PPC::V7, PPC::V8, PPC::V9, in CC_AIX()
6547 PPC::V10, PPC::V11, PPC::V12, PPC::V13}; in CC_AIX()
6714 if (GPRs[NextRegIndex] == PPC::R9) { in CC_AIX()
6719 const unsigned FirstReg = State.AllocateReg(PPC::R9); in CC_AIX()
6720 const unsigned SecondReg = State.AllocateReg(PPC::R10); in CC_AIX()
6762 return IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in getRegClassForSVT()
6764 return HasP8Vector ? &PPC::VSSRCRegClass : &PPC::F4RCRegClass; in getRegClassForSVT()
6766 return HasVSX ? &PPC::VSFRCRegClass : &PPC::F8RCRegClass; in getRegClassForSVT()
6774 return &PPC::VRRCRegClass; in getRegClassForSVT()
6797 if (PPC::GPRCRegClass.contains(Reg)) { in mapArgRegToOffsetAIX()
6798 assert(Reg >= PPC::R3 && Reg <= PPC::R10 && in mapArgRegToOffsetAIX()
6800 return LASize + 4 * (Reg - PPC::R3); in mapArgRegToOffsetAIX()
6803 if (PPC::G8RCRegClass.contains(Reg)) { in mapArgRegToOffsetAIX()
6804 assert(Reg >= PPC::X3 && Reg <= PPC::X10 && in mapArgRegToOffsetAIX()
6806 return LASize + 8 * (Reg - PPC::X3); in mapArgRegToOffsetAIX()
7034 IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in LowerFormalArguments_AIX()
7121 static const MCPhysReg GPR_32[] = {PPC::R3, PPC::R4, PPC::R5, PPC::R6, in LowerFormalArguments_AIX()
7122 PPC::R7, PPC::R8, PPC::R9, PPC::R10}; in LowerFormalArguments_AIX()
7124 static const MCPhysReg GPR_64[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6, in LowerFormalArguments_AIX()
7125 PPC::X7, PPC::X8, PPC::X9, PPC::X10}; in LowerFormalArguments_AIX()
7136 IsPPC64 ? MF.addLiveIn(GPR_64[GPRIndex], &PPC::G8RCRegClass) in LowerFormalArguments_AIX()
7137 : MF.addLiveIn(GPR_32[GPRIndex], &PPC::GPRCRegClass); in LowerFormalArguments_AIX()
7213 const SDValue StackPtr = IsPPC64 ? DAG.getRegister(PPC::X1, MVT::i64) in LowerCall_AIX()
7214 : DAG.getRegister(PPC::R1, MVT::i32); in LowerCall_AIX()
7582 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; in LowerSTACKRESTORE()
9759 (PPC::isSplatShuffleMask(SVOp, 4) || PPC::isSplatShuffleMask(SVOp, 8)) && in LowerVECTOR_SHUFFLE()
9761 bool IsFourByte = PPC::isSplatShuffleMask(SVOp, 4); in LowerVECTOR_SHUFFLE()
9763 PPC::getSplatIdxForPPCMnemonics(SVOp, IsFourByte ? 4 : 8, DAG); in LowerVECTOR_SHUFFLE()
9811 PPC::isXXINSERTWMask(SVOp, ShiftElts, InsertAtByte, Swap, in LowerVECTOR_SHUFFLE()
9845 PPC::isXXSLDWIShuffleMask(SVOp, ShiftElts, Swap, isLittleEndian)) { in LowerVECTOR_SHUFFLE()
9858 PPC::isXXPERMDIShuffleMask(SVOp, ShiftElts, Swap, isLittleEndian)) { in LowerVECTOR_SHUFFLE()
9871 if (PPC::isXXBRHShuffleMask(SVOp)) { in LowerVECTOR_SHUFFLE()
9875 } else if (PPC::isXXBRWShuffleMask(SVOp)) { in LowerVECTOR_SHUFFLE()
9879 } else if (PPC::isXXBRDShuffleMask(SVOp)) { in LowerVECTOR_SHUFFLE()
9883 } else if (PPC::isXXBRQShuffleMask(SVOp)) { in LowerVECTOR_SHUFFLE()
9891 if (V2.isUndef() && PPC::isSplatShuffleMask(SVOp, 4)) { in LowerVECTOR_SHUFFLE()
9892 int SplatIdx = PPC::getSplatIdxForPPCMnemonics(SVOp, 4, DAG); in LowerVECTOR_SHUFFLE()
9901 if (V2.isUndef() && PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) == 8) { in LowerVECTOR_SHUFFLE()
9912 if (PPC::isSplatShuffleMask(SVOp, 1) || in LowerVECTOR_SHUFFLE()
9913 PPC::isSplatShuffleMask(SVOp, 2) || in LowerVECTOR_SHUFFLE()
9914 PPC::isSplatShuffleMask(SVOp, 4) || in LowerVECTOR_SHUFFLE()
9915 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) || in LowerVECTOR_SHUFFLE()
9916 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) || in LowerVECTOR_SHUFFLE()
9917 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 || in LowerVECTOR_SHUFFLE()
9918 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) || in LowerVECTOR_SHUFFLE()
9919 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) || in LowerVECTOR_SHUFFLE()
9920 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) || in LowerVECTOR_SHUFFLE()
9921 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) || in LowerVECTOR_SHUFFLE()
9922 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) || in LowerVECTOR_SHUFFLE()
9923 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) || in LowerVECTOR_SHUFFLE()
9925 PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) || in LowerVECTOR_SHUFFLE()
9926 PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) || in LowerVECTOR_SHUFFLE()
9927 PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)))) { in LowerVECTOR_SHUFFLE()
9936 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) || in LowerVECTOR_SHUFFLE()
9937 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) || in LowerVECTOR_SHUFFLE()
9938 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 || in LowerVECTOR_SHUFFLE()
9939 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) || in LowerVECTOR_SHUFFLE()
9940 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) || in LowerVECTOR_SHUFFLE()
9941 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) || in LowerVECTOR_SHUFFLE()
9942 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) || in LowerVECTOR_SHUFFLE()
9943 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) || in LowerVECTOR_SHUFFLE()
9944 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) || in LowerVECTOR_SHUFFLE()
9946 PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) || in LowerVECTOR_SHUFFLE()
9947 PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) || in LowerVECTOR_SHUFFLE()
9948 PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG)))) in LowerVECTOR_SHUFFLE()
10349 return DAG.getRegister(PPC::X13, MVT::i64); in LowerINTRINSIC_WO_CHAIN()
10350 return DAG.getRegister(PPC::R2, MVT::i32); in LowerINTRINSIC_WO_CHAIN()
10400 DAG.getRegister(PPC::CR6, MVT::i32), in LowerINTRINSIC_WO_CHAIN()
10446 return SDValue(DAG.getMachineNode(PPC::CFENCE8, DL, MVT::Other, in LowerINTRINSIC_VOID()
11037 auto LoadMnemonic = PPC::LDARX; in EmitAtomicBinary()
11038 auto StoreMnemonic = PPC::STDCX; in EmitAtomicBinary()
11043 LoadMnemonic = PPC::LBARX; in EmitAtomicBinary()
11044 StoreMnemonic = PPC::STBCX; in EmitAtomicBinary()
11048 LoadMnemonic = PPC::LHARX; in EmitAtomicBinary()
11049 StoreMnemonic = PPC::STHCX; in EmitAtomicBinary()
11053 LoadMnemonic = PPC::LWARX; in EmitAtomicBinary()
11054 StoreMnemonic = PPC::STWCX; in EmitAtomicBinary()
11057 LoadMnemonic = PPC::LDARX; in EmitAtomicBinary()
11058 StoreMnemonic = PPC::STDCX; in EmitAtomicBinary()
11086 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass in EmitAtomicBinary()
11087 : &PPC::GPRCRegClass); in EmitAtomicBinary()
11118 if (CmpOpcode == PPC::CMPW && AtomicSize < 4) { in EmitAtomicBinary()
11119 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitAtomicBinary()
11120 BuildMI(BB, dl, TII->get(AtomicSize == 1 ? PPC::EXTSB : PPC::EXTSH), in EmitAtomicBinary()
11122 BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0) in EmitAtomicBinary()
11125 BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0) in EmitAtomicBinary()
11128 BuildMI(BB, dl, TII->get(PPC::BCC)) in EmitAtomicBinary()
11129 .addImm(CmpPred).addReg(PPC::CR0).addMBB(exitMBB); in EmitAtomicBinary()
11136 BuildMI(BB, dl, TII->get(PPC::BCC)) in EmitAtomicBinary()
11137 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); in EmitAtomicBinary()
11151 case PPC::COPY: in isSignExtended()
11153 case PPC::LHA: in isSignExtended()
11154 case PPC::LHA8: in isSignExtended()
11155 case PPC::LHAU: in isSignExtended()
11156 case PPC::LHAU8: in isSignExtended()
11157 case PPC::LHAUX: in isSignExtended()
11158 case PPC::LHAUX8: in isSignExtended()
11159 case PPC::LHAX: in isSignExtended()
11160 case PPC::LHAX8: in isSignExtended()
11161 case PPC::LWA: in isSignExtended()
11162 case PPC::LWAUX: in isSignExtended()
11163 case PPC::LWAX: in isSignExtended()
11164 case PPC::LWAX_32: in isSignExtended()
11165 case PPC::LWA_32: in isSignExtended()
11166 case PPC::PLHA: in isSignExtended()
11167 case PPC::PLHA8: in isSignExtended()
11168 case PPC::PLHA8pc: in isSignExtended()
11169 case PPC::PLHApc: in isSignExtended()
11170 case PPC::PLWA: in isSignExtended()
11171 case PPC::PLWA8: in isSignExtended()
11172 case PPC::PLWA8pc: in isSignExtended()
11173 case PPC::PLWApc: in isSignExtended()
11174 case PPC::EXTSB: in isSignExtended()
11175 case PPC::EXTSB8: in isSignExtended()
11176 case PPC::EXTSB8_32_64: in isSignExtended()
11177 case PPC::EXTSB8_rec: in isSignExtended()
11178 case PPC::EXTSB_rec: in isSignExtended()
11179 case PPC::EXTSH: in isSignExtended()
11180 case PPC::EXTSH8: in isSignExtended()
11181 case PPC::EXTSH8_32_64: in isSignExtended()
11182 case PPC::EXTSH8_rec: in isSignExtended()
11183 case PPC::EXTSH_rec: in isSignExtended()
11184 case PPC::EXTSW: in isSignExtended()
11185 case PPC::EXTSWSLI: in isSignExtended()
11186 case PPC::EXTSWSLI_32_64: in isSignExtended()
11187 case PPC::EXTSWSLI_32_64_rec: in isSignExtended()
11188 case PPC::EXTSWSLI_rec: in isSignExtended()
11189 case PPC::EXTSW_32: in isSignExtended()
11190 case PPC::EXTSW_32_64: in isSignExtended()
11191 case PPC::EXTSW_32_64_rec: in isSignExtended()
11192 case PPC::EXTSW_rec: in isSignExtended()
11193 case PPC::SRAW: in isSignExtended()
11194 case PPC::SRAWI: in isSignExtended()
11195 case PPC::SRAWI_rec: in isSignExtended()
11196 case PPC::SRAW_rec: in isSignExtended()
11218 if (CmpOpcode == PPC::CMPW && !IsSignExtended) { in EmitPartwordAtomicBinary()
11219 Register ValueReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitPartwordAtomicBinary()
11220 BuildMI(*BB, MI, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueReg) in EmitPartwordAtomicBinary()
11235 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitPartwordAtomicBinary()
11257 is64bit ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in EmitPartwordAtomicBinary()
11258 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in EmitPartwordAtomicBinary()
11304 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) in EmitPartwordAtomicBinary()
11312 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg) in EmitPartwordAtomicBinary()
11313 .addReg(Ptr1Reg, 0, is64bit ? PPC::sub_32 : 0) in EmitPartwordAtomicBinary()
11318 BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg) in EmitPartwordAtomicBinary()
11322 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitPartwordAtomicBinary()
11327 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitPartwordAtomicBinary()
11332 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg).addReg(incr).addReg(ShiftReg); in EmitPartwordAtomicBinary()
11334 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); in EmitPartwordAtomicBinary()
11336 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); in EmitPartwordAtomicBinary()
11337 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) in EmitPartwordAtomicBinary()
11341 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitPartwordAtomicBinary()
11346 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) in EmitPartwordAtomicBinary()
11353 BuildMI(BB, dl, TII->get(PPC::ANDC), Tmp2Reg) in EmitPartwordAtomicBinary()
11356 BuildMI(BB, dl, TII->get(PPC::AND), Tmp3Reg).addReg(TmpReg).addReg(MaskReg); in EmitPartwordAtomicBinary()
11361 BuildMI(BB, dl, TII->get(PPC::AND), SReg) in EmitPartwordAtomicBinary()
11366 if (CmpOpcode == PPC::CMPW) { in EmitPartwordAtomicBinary()
11368 BuildMI(BB, dl, TII->get(PPC::SRW), ValueReg) in EmitPartwordAtomicBinary()
11372 BuildMI(BB, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueSReg) in EmitPartwordAtomicBinary()
11377 BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0) in EmitPartwordAtomicBinary()
11380 BuildMI(BB, dl, TII->get(PPC::BCC)) in EmitPartwordAtomicBinary()
11382 .addReg(PPC::CR0) in EmitPartwordAtomicBinary()
11388 BuildMI(BB, dl, TII->get(PPC::OR), Tmp4Reg).addReg(Tmp3Reg).addReg(Tmp2Reg); in EmitPartwordAtomicBinary()
11389 BuildMI(BB, dl, TII->get(PPC::STWCX)) in EmitPartwordAtomicBinary()
11393 BuildMI(BB, dl, TII->get(PPC::BCC)) in EmitPartwordAtomicBinary()
11394 .addImm(PPC::PRED_NE) in EmitPartwordAtomicBinary()
11395 .addReg(PPC::CR0) in EmitPartwordAtomicBinary()
11405 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::RLWINM), dest) in EmitPartwordAtomicBinary()
11410 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), SrwDestReg) in EmitPartwordAtomicBinary()
11490 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD)) in emitEHSjLjSetJmp()
11491 .addReg(PPC::X2) in emitEHSjLjSetJmp()
11501 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1; in emitEHSjLjSetJmp()
11503 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP; in emitEHSjLjSetJmp()
11506 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW)) in emitEHSjLjSetJmp()
11513 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB); in emitEHSjLjSetJmp()
11516 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1); in emitEHSjLjSetJmp()
11518 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup)) in emitEHSjLjSetJmp()
11520 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB); in emitEHSjLjSetJmp()
11529 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg); in emitEHSjLjSetJmp()
11533 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD)) in emitEHSjLjSetJmp()
11538 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW)) in emitEHSjLjSetJmp()
11545 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0); in emitEHSjLjSetJmp()
11550 TII->get(PPC::PHI), DstReg) in emitEHSjLjSetJmp()
11572 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in emitEHSjLjLongJmp()
11575 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31; in emitEHSjLjLongJmp()
11576 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1; in emitEHSjLjLongJmp()
11579 ? PPC::X30 in emitEHSjLjLongJmp()
11580 : (Subtarget.isSVR4ABI() && isPositionIndependent() ? PPC::R29 in emitEHSjLjLongJmp()
11581 : PPC::R30); in emitEHSjLjLongJmp()
11596 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP) in emitEHSjLjLongJmp()
11600 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP) in emitEHSjLjLongJmp()
11608 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp) in emitEHSjLjLongJmp()
11612 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp) in emitEHSjLjLongJmp()
11620 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP) in emitEHSjLjLongJmp()
11624 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP) in emitEHSjLjLongJmp()
11632 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP) in emitEHSjLjLongJmp()
11636 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP) in emitEHSjLjLongJmp()
11645 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2) in emitEHSjLjLongJmp()
11653 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp); in emitEHSjLjLongJmp()
11654 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR)); in emitEHSjLjLongJmp()
11731 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in emitProbedAlloca()
11732 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in emitProbedAlloca()
11736 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1; in emitProbedAlloca()
11747 isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_64 : PPC::PREPARE_PROBED_ALLOCA_32; in emitProbedAlloca()
11753 ProbeOpc = isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 in emitProbedAlloca()
11754 : PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32; in emitProbedAlloca()
11762 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::ADD8 : PPC::ADD4), in emitProbedAlloca()
11773 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS), TempReg) in emitProbedAlloca()
11775 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::ORI8 : PPC::ORI), in emitProbedAlloca()
11780 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LI8 : PPC::LI), ScratchReg) in emitProbedAlloca()
11786 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::DIVD : PPC::DIVW), Div) in emitProbedAlloca()
11790 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::MULLD : PPC::MULLW), Mul) in emitProbedAlloca()
11794 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::SUBF8 : PPC::SUBF), NegMod) in emitProbedAlloca()
11797 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg) in emitProbedAlloca()
11805 Register CmpResult = MRI.createVirtualRegister(&PPC::CRRCRegClass); in emitProbedAlloca()
11806 BuildMI(TestMBB, DL, TII->get(isPPC64 ? PPC::CMPD : PPC::CMPW), CmpResult) in emitProbedAlloca()
11809 BuildMI(TestMBB, DL, TII->get(PPC::BCC)) in emitProbedAlloca()
11810 .addImm(PPC::PRED_EQ) in emitProbedAlloca()
11820 BuildMI(BlockMBB, DL, TII->get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg) in emitProbedAlloca()
11824 BuildMI(BlockMBB, DL, TII->get(PPC::B)).addMBB(TestMBB); in emitProbedAlloca()
11833 TII->get(isPPC64 ? PPC::DYNAREAOFFSET8 : PPC::DYNAREAOFFSET), in emitProbedAlloca()
11837 BuildMI(TailMBB, DL, TII->get(isPPC64 ? PPC::ADD8 : PPC::ADD4), DstReg) in emitProbedAlloca()
11867 MI.addOperand(MachineOperand::CreateReg(PPC::X2, false, true)); in EmitInstrWithCustomInserter()
11873 if (MI.getOpcode() == PPC::EH_SjLj_SetJmp32 || in EmitInstrWithCustomInserter()
11874 MI.getOpcode() == PPC::EH_SjLj_SetJmp64) { in EmitInstrWithCustomInserter()
11876 } else if (MI.getOpcode() == PPC::EH_SjLj_LongJmp32 || in EmitInstrWithCustomInserter()
11877 MI.getOpcode() == PPC::EH_SjLj_LongJmp64) { in EmitInstrWithCustomInserter()
11890 if (MI.getOpcode() == PPC::SELECT_CC_I4 || in EmitInstrWithCustomInserter()
11891 MI.getOpcode() == PPC::SELECT_CC_I8 || MI.getOpcode() == PPC::SELECT_I4 || in EmitInstrWithCustomInserter()
11892 MI.getOpcode() == PPC::SELECT_I8) { in EmitInstrWithCustomInserter()
11894 if (MI.getOpcode() == PPC::SELECT_CC_I4 || in EmitInstrWithCustomInserter()
11895 MI.getOpcode() == PPC::SELECT_CC_I8) in EmitInstrWithCustomInserter()
11898 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); in EmitInstrWithCustomInserter()
11904 } else if (MI.getOpcode() == PPC::SELECT_CC_F4 || in EmitInstrWithCustomInserter()
11905 MI.getOpcode() == PPC::SELECT_CC_F8 || in EmitInstrWithCustomInserter()
11906 MI.getOpcode() == PPC::SELECT_CC_F16 || in EmitInstrWithCustomInserter()
11907 MI.getOpcode() == PPC::SELECT_CC_VRRC || in EmitInstrWithCustomInserter()
11908 MI.getOpcode() == PPC::SELECT_CC_VSFRC || in EmitInstrWithCustomInserter()
11909 MI.getOpcode() == PPC::SELECT_CC_VSSRC || in EmitInstrWithCustomInserter()
11910 MI.getOpcode() == PPC::SELECT_CC_VSRC || in EmitInstrWithCustomInserter()
11911 MI.getOpcode() == PPC::SELECT_CC_SPE4 || in EmitInstrWithCustomInserter()
11912 MI.getOpcode() == PPC::SELECT_CC_SPE || in EmitInstrWithCustomInserter()
11913 MI.getOpcode() == PPC::SELECT_F4 || in EmitInstrWithCustomInserter()
11914 MI.getOpcode() == PPC::SELECT_F8 || in EmitInstrWithCustomInserter()
11915 MI.getOpcode() == PPC::SELECT_F16 || in EmitInstrWithCustomInserter()
11916 MI.getOpcode() == PPC::SELECT_SPE || in EmitInstrWithCustomInserter()
11917 MI.getOpcode() == PPC::SELECT_SPE4 || in EmitInstrWithCustomInserter()
11918 MI.getOpcode() == PPC::SELECT_VRRC || in EmitInstrWithCustomInserter()
11919 MI.getOpcode() == PPC::SELECT_VSFRC || in EmitInstrWithCustomInserter()
11920 MI.getOpcode() == PPC::SELECT_VSSRC || in EmitInstrWithCustomInserter()
11921 MI.getOpcode() == PPC::SELECT_VSRC) { in EmitInstrWithCustomInserter()
11948 if (MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8 || in EmitInstrWithCustomInserter()
11949 MI.getOpcode() == PPC::SELECT_F4 || MI.getOpcode() == PPC::SELECT_F8 || in EmitInstrWithCustomInserter()
11950 MI.getOpcode() == PPC::SELECT_F16 || in EmitInstrWithCustomInserter()
11951 MI.getOpcode() == PPC::SELECT_SPE4 || in EmitInstrWithCustomInserter()
11952 MI.getOpcode() == PPC::SELECT_SPE || in EmitInstrWithCustomInserter()
11953 MI.getOpcode() == PPC::SELECT_VRRC || in EmitInstrWithCustomInserter()
11954 MI.getOpcode() == PPC::SELECT_VSFRC || in EmitInstrWithCustomInserter()
11955 MI.getOpcode() == PPC::SELECT_VSSRC || in EmitInstrWithCustomInserter()
11956 MI.getOpcode() == PPC::SELECT_VSRC) { in EmitInstrWithCustomInserter()
11957 BuildMI(BB, dl, TII->get(PPC::BC)) in EmitInstrWithCustomInserter()
11962 BuildMI(BB, dl, TII->get(PPC::BCC)) in EmitInstrWithCustomInserter()
11980 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::PHI), MI.getOperand(0).getReg()) in EmitInstrWithCustomInserter()
11985 } else if (MI.getOpcode() == PPC::ReadTB) { in EmitInstrWithCustomInserter()
12013 Register ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitInstrWithCustomInserter()
12017 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269); in EmitInstrWithCustomInserter()
12018 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268); in EmitInstrWithCustomInserter()
12019 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269); in EmitInstrWithCustomInserter()
12021 Register CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass); in EmitInstrWithCustomInserter()
12023 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg) in EmitInstrWithCustomInserter()
12026 BuildMI(BB, dl, TII->get(PPC::BCC)) in EmitInstrWithCustomInserter()
12027 .addImm(PPC::PRED_NE) in EmitInstrWithCustomInserter()
12033 } else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I8) in EmitInstrWithCustomInserter()
12034 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4); in EmitInstrWithCustomInserter()
12035 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I16) in EmitInstrWithCustomInserter()
12036 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4); in EmitInstrWithCustomInserter()
12037 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I32) in EmitInstrWithCustomInserter()
12038 BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4); in EmitInstrWithCustomInserter()
12039 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) in EmitInstrWithCustomInserter()
12040 BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8); in EmitInstrWithCustomInserter()
12042 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I8) in EmitInstrWithCustomInserter()
12043 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND); in EmitInstrWithCustomInserter()
12044 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I16) in EmitInstrWithCustomInserter()
12045 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND); in EmitInstrWithCustomInserter()
12046 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I32) in EmitInstrWithCustomInserter()
12047 BB = EmitAtomicBinary(MI, BB, 4, PPC::AND); in EmitInstrWithCustomInserter()
12048 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I64) in EmitInstrWithCustomInserter()
12049 BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8); in EmitInstrWithCustomInserter()
12051 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I8) in EmitInstrWithCustomInserter()
12052 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR); in EmitInstrWithCustomInserter()
12053 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I16) in EmitInstrWithCustomInserter()
12054 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR); in EmitInstrWithCustomInserter()
12055 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I32) in EmitInstrWithCustomInserter()
12056 BB = EmitAtomicBinary(MI, BB, 4, PPC::OR); in EmitInstrWithCustomInserter()
12057 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I64) in EmitInstrWithCustomInserter()
12058 BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8); in EmitInstrWithCustomInserter()
12060 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I8) in EmitInstrWithCustomInserter()
12061 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR); in EmitInstrWithCustomInserter()
12062 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I16) in EmitInstrWithCustomInserter()
12063 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR); in EmitInstrWithCustomInserter()
12064 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I32) in EmitInstrWithCustomInserter()
12065 BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR); in EmitInstrWithCustomInserter()
12066 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I64) in EmitInstrWithCustomInserter()
12067 BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8); in EmitInstrWithCustomInserter()
12069 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I8) in EmitInstrWithCustomInserter()
12070 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND); in EmitInstrWithCustomInserter()
12071 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I16) in EmitInstrWithCustomInserter()
12072 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND); in EmitInstrWithCustomInserter()
12073 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I32) in EmitInstrWithCustomInserter()
12074 BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND); in EmitInstrWithCustomInserter()
12075 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I64) in EmitInstrWithCustomInserter()
12076 BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8); in EmitInstrWithCustomInserter()
12078 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I8) in EmitInstrWithCustomInserter()
12079 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF); in EmitInstrWithCustomInserter()
12080 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I16) in EmitInstrWithCustomInserter()
12081 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF); in EmitInstrWithCustomInserter()
12082 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I32) in EmitInstrWithCustomInserter()
12083 BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF); in EmitInstrWithCustomInserter()
12084 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I64) in EmitInstrWithCustomInserter()
12085 BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8); in EmitInstrWithCustomInserter()
12087 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I8) in EmitInstrWithCustomInserter()
12088 BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPW, PPC::PRED_GE); in EmitInstrWithCustomInserter()
12089 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I16) in EmitInstrWithCustomInserter()
12090 BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPW, PPC::PRED_GE); in EmitInstrWithCustomInserter()
12091 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I32) in EmitInstrWithCustomInserter()
12092 BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPW, PPC::PRED_GE); in EmitInstrWithCustomInserter()
12093 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I64) in EmitInstrWithCustomInserter()
12094 BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPD, PPC::PRED_GE); in EmitInstrWithCustomInserter()
12096 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I8) in EmitInstrWithCustomInserter()
12097 BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPW, PPC::PRED_LE); in EmitInstrWithCustomInserter()
12098 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I16) in EmitInstrWithCustomInserter()
12099 BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPW, PPC::PRED_LE); in EmitInstrWithCustomInserter()
12100 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I32) in EmitInstrWithCustomInserter()
12101 BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPW, PPC::PRED_LE); in EmitInstrWithCustomInserter()
12102 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I64) in EmitInstrWithCustomInserter()
12103 BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPD, PPC::PRED_LE); in EmitInstrWithCustomInserter()
12105 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I8) in EmitInstrWithCustomInserter()
12106 BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPLW, PPC::PRED_GE); in EmitInstrWithCustomInserter()
12107 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I16) in EmitInstrWithCustomInserter()
12108 BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPLW, PPC::PRED_GE); in EmitInstrWithCustomInserter()
12109 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I32) in EmitInstrWithCustomInserter()
12110 BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPLW, PPC::PRED_GE); in EmitInstrWithCustomInserter()
12111 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I64) in EmitInstrWithCustomInserter()
12112 BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPLD, PPC::PRED_GE); in EmitInstrWithCustomInserter()
12114 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I8) in EmitInstrWithCustomInserter()
12115 BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPLW, PPC::PRED_LE); in EmitInstrWithCustomInserter()
12116 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I16) in EmitInstrWithCustomInserter()
12117 BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPLW, PPC::PRED_LE); in EmitInstrWithCustomInserter()
12118 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I32) in EmitInstrWithCustomInserter()
12119 BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPLW, PPC::PRED_LE); in EmitInstrWithCustomInserter()
12120 else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I64) in EmitInstrWithCustomInserter()
12121 BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPLD, PPC::PRED_LE); in EmitInstrWithCustomInserter()
12123 else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I8) in EmitInstrWithCustomInserter()
12125 else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I16) in EmitInstrWithCustomInserter()
12127 else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I32) in EmitInstrWithCustomInserter()
12129 else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I64) in EmitInstrWithCustomInserter()
12131 else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 || in EmitInstrWithCustomInserter()
12132 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 || in EmitInstrWithCustomInserter()
12134 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) || in EmitInstrWithCustomInserter()
12136 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) { in EmitInstrWithCustomInserter()
12137 bool is64bit = MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I64; in EmitInstrWithCustomInserter()
12139 auto LoadMnemonic = PPC::LDARX; in EmitInstrWithCustomInserter()
12140 auto StoreMnemonic = PPC::STDCX; in EmitInstrWithCustomInserter()
12144 case PPC::ATOMIC_CMP_SWAP_I8: in EmitInstrWithCustomInserter()
12145 LoadMnemonic = PPC::LBARX; in EmitInstrWithCustomInserter()
12146 StoreMnemonic = PPC::STBCX; in EmitInstrWithCustomInserter()
12149 case PPC::ATOMIC_CMP_SWAP_I16: in EmitInstrWithCustomInserter()
12150 LoadMnemonic = PPC::LHARX; in EmitInstrWithCustomInserter()
12151 StoreMnemonic = PPC::STHCX; in EmitInstrWithCustomInserter()
12154 case PPC::ATOMIC_CMP_SWAP_I32: in EmitInstrWithCustomInserter()
12155 LoadMnemonic = PPC::LWARX; in EmitInstrWithCustomInserter()
12156 StoreMnemonic = PPC::STWCX; in EmitInstrWithCustomInserter()
12158 case PPC::ATOMIC_CMP_SWAP_I64: in EmitInstrWithCustomInserter()
12159 LoadMnemonic = PPC::LDARX; in EmitInstrWithCustomInserter()
12160 StoreMnemonic = PPC::STDCX; in EmitInstrWithCustomInserter()
12200 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) in EmitInstrWithCustomInserter()
12203 BuildMI(BB, dl, TII->get(PPC::BCC)) in EmitInstrWithCustomInserter()
12204 .addImm(PPC::PRED_NE) in EmitInstrWithCustomInserter()
12205 .addReg(PPC::CR0) in EmitInstrWithCustomInserter()
12215 BuildMI(BB, dl, TII->get(PPC::BCC)) in EmitInstrWithCustomInserter()
12216 .addImm(PPC::PRED_NE) in EmitInstrWithCustomInserter()
12217 .addReg(PPC::CR0) in EmitInstrWithCustomInserter()
12219 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); in EmitInstrWithCustomInserter()
12233 } else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 || in EmitInstrWithCustomInserter()
12234 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) { in EmitInstrWithCustomInserter()
12240 bool is8bit = MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8; in EmitInstrWithCustomInserter()
12263 is64bit ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in EmitInstrWithCustomInserter()
12264 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in EmitInstrWithCustomInserter()
12282 Register ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitInstrWithCustomInserter()
12317 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg) in EmitInstrWithCustomInserter()
12326 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg) in EmitInstrWithCustomInserter()
12327 .addReg(Ptr1Reg, 0, is64bit ? PPC::sub_32 : 0) in EmitInstrWithCustomInserter()
12332 BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg) in EmitInstrWithCustomInserter()
12336 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg) in EmitInstrWithCustomInserter()
12341 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg) in EmitInstrWithCustomInserter()
12346 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) in EmitInstrWithCustomInserter()
12349 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) in EmitInstrWithCustomInserter()
12353 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255); in EmitInstrWithCustomInserter()
12355 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0); in EmitInstrWithCustomInserter()
12356 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg) in EmitInstrWithCustomInserter()
12360 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitInstrWithCustomInserter()
12363 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg) in EmitInstrWithCustomInserter()
12366 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg) in EmitInstrWithCustomInserter()
12371 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg) in EmitInstrWithCustomInserter()
12374 BuildMI(BB, dl, TII->get(PPC::AND), TmpReg) in EmitInstrWithCustomInserter()
12377 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) in EmitInstrWithCustomInserter()
12380 BuildMI(BB, dl, TII->get(PPC::BCC)) in EmitInstrWithCustomInserter()
12381 .addImm(PPC::PRED_NE) in EmitInstrWithCustomInserter()
12382 .addReg(PPC::CR0) in EmitInstrWithCustomInserter()
12388 BuildMI(BB, dl, TII->get(PPC::ANDC), Tmp2Reg) in EmitInstrWithCustomInserter()
12391 BuildMI(BB, dl, TII->get(PPC::OR), Tmp4Reg) in EmitInstrWithCustomInserter()
12394 BuildMI(BB, dl, TII->get(PPC::STWCX)) in EmitInstrWithCustomInserter()
12398 BuildMI(BB, dl, TII->get(PPC::BCC)) in EmitInstrWithCustomInserter()
12399 .addImm(PPC::PRED_NE) in EmitInstrWithCustomInserter()
12400 .addReg(PPC::CR0) in EmitInstrWithCustomInserter()
12402 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB); in EmitInstrWithCustomInserter()
12407 BuildMI(BB, dl, TII->get(PPC::STWCX)) in EmitInstrWithCustomInserter()
12416 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest) in EmitInstrWithCustomInserter()
12419 } else if (MI.getOpcode() == PPC::FADDrtz) { in EmitInstrWithCustomInserter()
12429 Register MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); in EmitInstrWithCustomInserter()
12432 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg); in EmitInstrWithCustomInserter()
12435 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)) in EmitInstrWithCustomInserter()
12437 .addReg(PPC::RM, RegState::ImplicitDefine); in EmitInstrWithCustomInserter()
12439 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)) in EmitInstrWithCustomInserter()
12441 .addReg(PPC::RM, RegState::ImplicitDefine); in EmitInstrWithCustomInserter()
12444 auto MIB = BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest) in EmitInstrWithCustomInserter()
12451 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg); in EmitInstrWithCustomInserter()
12452 } else if (MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT || in EmitInstrWithCustomInserter()
12453 MI.getOpcode() == PPC::ANDI_rec_1_GT_BIT || in EmitInstrWithCustomInserter()
12454 MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT8 || in EmitInstrWithCustomInserter()
12455 MI.getOpcode() == PPC::ANDI_rec_1_GT_BIT8) { in EmitInstrWithCustomInserter()
12456 unsigned Opcode = (MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT8 || in EmitInstrWithCustomInserter()
12457 MI.getOpcode() == PPC::ANDI_rec_1_GT_BIT8) in EmitInstrWithCustomInserter()
12458 ? PPC::ANDI8_rec in EmitInstrWithCustomInserter()
12459 : PPC::ANDI_rec; in EmitInstrWithCustomInserter()
12460 bool IsEQ = (MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT || in EmitInstrWithCustomInserter()
12461 MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT8); in EmitInstrWithCustomInserter()
12465 Opcode == PPC::ANDI_rec ? &PPC::GPRCRegClass : &PPC::G8RCRegClass); in EmitInstrWithCustomInserter()
12473 .addReg(IsEQ ? PPC::CR0EQ : PPC::CR0GT); in EmitInstrWithCustomInserter()
12474 } else if (MI.getOpcode() == PPC::TCHECK_RET) { in EmitInstrWithCustomInserter()
12477 Register CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass); in EmitInstrWithCustomInserter()
12478 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg); in EmitInstrWithCustomInserter()
12482 } else if (MI.getOpcode() == PPC::TBEGIN_RET) { in EmitInstrWithCustomInserter()
12485 BuildMI(*BB, MI, Dl, TII->get(PPC::TBEGIN)).addImm(Imm); in EmitInstrWithCustomInserter()
12488 .addReg(PPC::CR0EQ); in EmitInstrWithCustomInserter()
12489 } else if (MI.getOpcode() == PPC::SETRNDi) { in EmitInstrWithCustomInserter()
12494 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), OldFPSCRReg); in EmitInstrWithCustomInserter()
12506 BuildMI(*BB, MI, dl, TII->get((Mode & 1) ? PPC::MTFSB1 : PPC::MTFSB0)) in EmitInstrWithCustomInserter()
12508 .addReg(PPC::RM, RegState::ImplicitDefine); in EmitInstrWithCustomInserter()
12510 BuildMI(*BB, MI, dl, TII->get((Mode & 2) ? PPC::MTFSB1 : PPC::MTFSB0)) in EmitInstrWithCustomInserter()
12512 .addReg(PPC::RM, RegState::ImplicitDefine); in EmitInstrWithCustomInserter()
12513 } else if (MI.getOpcode() == PPC::SETRND) { in EmitInstrWithCustomInserter()
12527 unsigned StoreOp = PPC::STD, LoadOp = PPC::LFD; in EmitInstrWithCustomInserter()
12530 if (RC == &PPC::F8RCRegClass) { in EmitInstrWithCustomInserter()
12532 assert((RegInfo.getRegClass(DestReg) == &PPC::G8RCRegClass) && in EmitInstrWithCustomInserter()
12535 StoreOp = PPC::STFD; in EmitInstrWithCustomInserter()
12536 LoadOp = PPC::LD; in EmitInstrWithCustomInserter()
12539 assert((RegInfo.getRegClass(SrcReg) == &PPC::G8RCRegClass) && in EmitInstrWithCustomInserter()
12540 (RegInfo.getRegClass(DestReg) == &PPC::F8RCRegClass) && in EmitInstrWithCustomInserter()
12577 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), OldFPSCRReg); in EmitInstrWithCustomInserter()
12589 Register OldFPSCRTmpReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); in EmitInstrWithCustomInserter()
12593 Register ImDefReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); in EmitInstrWithCustomInserter()
12594 Register ExtSrcReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); in EmitInstrWithCustomInserter()
12600 BuildMI(*BB, MI, dl, TII->get(PPC::INSERT_SUBREG), ExtSrcReg) in EmitInstrWithCustomInserter()
12605 Register NewFPSCRTmpReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); in EmitInstrWithCustomInserter()
12606 BuildMI(*BB, MI, dl, TII->get(PPC::RLDIMI), NewFPSCRTmpReg) in EmitInstrWithCustomInserter()
12612 Register NewFPSCRReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); in EmitInstrWithCustomInserter()
12617 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)) in EmitInstrWithCustomInserter()
12622 } else if (MI.getOpcode() == PPC::SETFLM) { in EmitInstrWithCustomInserter()
12627 BuildMI(*BB, MI, Dl, TII->get(PPC::MFFS), OldFPSCRReg); in EmitInstrWithCustomInserter()
12631 BuildMI(*BB, MI, Dl, TII->get(PPC::MTFSF)) in EmitInstrWithCustomInserter()
12636 } else if (MI.getOpcode() == PPC::PROBED_ALLOCA_32 || in EmitInstrWithCustomInserter()
12637 MI.getOpcode() == PPC::PROBED_ALLOCA_64) { in EmitInstrWithCustomInserter()
12639 } else if (MI.getOpcode() == PPC::SPLIT_QUADWORD) { in EmitInstrWithCustomInserter()
12646 .addUse(Src, 0, PPC::sub_gp8_x1); in EmitInstrWithCustomInserter()
12649 .addUse(Src, 0, PPC::sub_gp8_x0); in EmitInstrWithCustomInserter()
12696 SDValue SRIdxVal = DAG.getTargetConstant(PPC::sub_eq, DL, MVT::i32); in getSqrtInputTest()
12763 case PPC::DIR_440: in combineRepeatedFPDivisors()
12764 case PPC::DIR_A2: in combineRepeatedFPDivisors()
12765 case PPC::DIR_E500: in combineRepeatedFPDivisors()
12766 case PPC::DIR_E500mc: in combineRepeatedFPDivisors()
12767 case PPC::DIR_E5500: in combineRepeatedFPDivisors()
15441 PPC::Predicate CompOpc; in PerformDAGCombine()
15445 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; in PerformDAGCombine()
15448 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; in PerformDAGCombine()
15451 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; in PerformDAGCombine()
15454 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; in PerformDAGCombine()
15460 DAG.getRegister(PPC::CR6, MVT::i32), in PerformDAGCombine()
15556 case PPC::DIR_970: in getPrefLoopAlignment()
15557 case PPC::DIR_PWR4: in getPrefLoopAlignment()
15558 case PPC::DIR_PWR5: in getPrefLoopAlignment()
15559 case PPC::DIR_PWR5X: in getPrefLoopAlignment()
15560 case PPC::DIR_PWR6: in getPrefLoopAlignment()
15561 case PPC::DIR_PWR6X: in getPrefLoopAlignment()
15562 case PPC::DIR_PWR7: in getPrefLoopAlignment()
15563 case PPC::DIR_PWR8: in getPrefLoopAlignment()
15564 case PPC::DIR_PWR9: in getPrefLoopAlignment()
15565 case PPC::DIR_PWR10: in getPrefLoopAlignment()
15566 case PPC::DIR_PWR_FUTURE: { in getPrefLoopAlignment()
15702 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass); in getRegForInlineAsmConstraint()
15703 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass); in getRegForInlineAsmConstraint()
15706 return std::make_pair(0U, &PPC::G8RCRegClass); in getRegForInlineAsmConstraint()
15707 return std::make_pair(0U, &PPC::GPRCRegClass); in getRegForInlineAsmConstraint()
15715 return std::make_pair(0U, &PPC::GPRCRegClass); in getRegForInlineAsmConstraint()
15717 return std::make_pair(0U, &PPC::SPERCRegClass); in getRegForInlineAsmConstraint()
15720 return std::make_pair(0U, &PPC::F4RCRegClass); in getRegForInlineAsmConstraint()
15722 return std::make_pair(0U, &PPC::F8RCRegClass); in getRegForInlineAsmConstraint()
15727 return std::make_pair(0U, &PPC::VRRCRegClass); in getRegForInlineAsmConstraint()
15730 return std::make_pair(0U, &PPC::CRRCRegClass); in getRegForInlineAsmConstraint()
15734 return std::make_pair(0U, &PPC::CRBITRCRegClass); in getRegForInlineAsmConstraint()
15741 return std::make_pair(0U, &PPC::VSRCRegClass); in getRegForInlineAsmConstraint()
15743 return std::make_pair(0U, &PPC::VSSRCRegClass); in getRegForInlineAsmConstraint()
15744 return std::make_pair(0U, &PPC::VSFRCRegClass); in getRegForInlineAsmConstraint()
15747 return std::make_pair(0U, &PPC::VSSRCRegClass); in getRegForInlineAsmConstraint()
15749 return std::make_pair(0U, &PPC::VSFRCRegClass); in getRegForInlineAsmConstraint()
15752 return std::make_pair(0U, &PPC::LR8RCRegClass); in getRegForInlineAsmConstraint()
15754 return std::make_pair(0U, &PPC::LRRCRegClass); in getRegForInlineAsmConstraint()
15768 return std::make_pair(PPC::VSL0 + VSNum, &PPC::VSRCRegClass); in getRegForInlineAsmConstraint()
15769 return std::make_pair(PPC::V0 + VSNum - 32, &PPC::VSRCRegClass); in getRegForInlineAsmConstraint()
15780 ? std::make_pair(PPC::R0 + RegNum, &PPC::GPRCRegClass) in getRegForInlineAsmConstraint()
15781 : std::make_pair(PPC::F0 + RegNum, &PPC::F4RCRegClass); in getRegForInlineAsmConstraint()
15784 ? std::make_pair(PPC::S0 + RegNum, &PPC::SPERCRegClass) in getRegForInlineAsmConstraint()
15785 : std::make_pair(PPC::F0 + RegNum, &PPC::F8RCRegClass); in getRegForInlineAsmConstraint()
15799 PPC::GPRCRegClass.contains(R.first)) in getRegForInlineAsmConstraint()
15801 PPC::sub_32, &PPC::G8RCRegClass), in getRegForInlineAsmConstraint()
15802 &PPC::G8RCRegClass); in getRegForInlineAsmConstraint()
15806 R.first = PPC::CR0; in getRegForInlineAsmConstraint()
15807 R.second = &PPC::CRRCRegClass; in getRegForInlineAsmConstraint()
15812 if (((R.first >= PPC::V20 && R.first <= PPC::V31) || in getRegForInlineAsmConstraint()
15813 (R.first >= PPC::VF20 && R.first <= PPC::VF31)) && in getRegForInlineAsmConstraint()
15814 (R.second == &PPC::VSRCRegClass || R.second == &PPC::VSFRCRegClass)) in getRegForInlineAsmConstraint()
15994 FrameReg = isPPC64 ? PPC::X1 : PPC::R1; in LowerFRAMEADDR()
15996 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP; in LowerFRAMEADDR()
16017 .Case("r1", is64Bit ? PPC::X1 : PPC::R1) in getRegisterByName()
16018 .Case("r2", isPPC64 ? Register() : PPC::R2) in getRegisterByName()
16019 .Case("r13", (is64Bit ? PPC::X13 : PPC::R13)) in getRegisterByName()
16393 PPC::X12, PPC::LR8, PPC::CTR8, 0 in getScratchRegisters()
16401 return Subtarget.isPPC64() ? PPC::X3 : PPC::R3; in getExceptionPointerRegister()
16406 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4; in getExceptionSelectorRegister()
16432 return PPC::createFastISel(FuncInfo, LibInfo); in createFastISel()
16866 case PPC::DIR_PWR8: in combineMUL()
16871 case PPC::DIR_PWR9: in combineMUL()
16872 case PPC::DIR_PWR10: in combineMUL()
16873 case PPC::DIR_PWR_FUTURE: in combineMUL()
17135 PPC::AddrMode PPCTargetLowering::getAddrModeForFlags(unsigned Flags) const { in getAddrModeForFlags()
17137 if (Flags == PPC::MOF_None) in getAddrModeForFlags()
17138 return PPC::AM_None; in getAddrModeForFlags()
17140 for (auto FlagSet : AddrModesMap.at(PPC::AM_DForm)) in getAddrModeForFlags()
17142 return PPC::AM_DForm; in getAddrModeForFlags()
17143 for (auto FlagSet : AddrModesMap.at(PPC::AM_DSForm)) in getAddrModeForFlags()
17145 return PPC::AM_DSForm; in getAddrModeForFlags()
17146 for (auto FlagSet : AddrModesMap.at(PPC::AM_DQForm)) in getAddrModeForFlags()
17148 return PPC::AM_DQForm; in getAddrModeForFlags()
17151 return PPC::AM_XForm; in getAddrModeForFlags()
17169 FlagSet &= ~PPC::MOF_RPlusSImm16Mult4; in setAlignFlagsForFI()
17171 FlagSet &= ~PPC::MOF_RPlusSImm16Mult16; in setAlignFlagsForFI()
17176 FlagSet |= PPC::MOF_RPlusSImm16Mult4; in setAlignFlagsForFI()
17178 FlagSet |= PPC::MOF_RPlusSImm16Mult16; in setAlignFlagsForFI()
17192 FlagSet |= PPC::MOF_RPlusSImm16Mult4; in computeFlagsForAddressComputation()
17194 FlagSet |= PPC::MOF_RPlusSImm16Mult16; in computeFlagsForAddressComputation()
17201 FlagSet |= PPC::MOF_AddrIsSImm32; in computeFlagsForAddressComputation()
17206 FlagSet |= PPC::MOF_RPlusSImm34; in computeFlagsForAddressComputation()
17208 FlagSet |= PPC::MOF_NotAddNorCst; in computeFlagsForAddressComputation()
17220 FlagSet |= PPC::MOF_RPlusSImm16; // Signed 16-bit immediates. in computeFlagsForAddressComputation()
17225 FlagSet |= PPC::MOF_RPlusSImm34; // Signed 34-bit immediates. in computeFlagsForAddressComputation()
17227 FlagSet |= PPC::MOF_RPlusR; // Register. in computeFlagsForAddressComputation()
17230 FlagSet |= PPC::MOF_RPlusLo; // PPCISD::Lo. in computeFlagsForAddressComputation()
17232 FlagSet |= PPC::MOF_RPlusR; in computeFlagsForAddressComputation()
17235 FlagSet |= PPC::MOF_NotAddNorCst; in computeFlagsForAddressComputation()
17243 unsigned FlagSet = PPC::MOF_None; in computeMOFlags()
17247 FlagSet |= PPC::MOF_SubtargetBeforeP9; in computeMOFlags()
17249 FlagSet |= PPC::MOF_SubtargetP9; in computeMOFlags()
17251 FlagSet |= PPC::MOF_SubtargetP10; in computeMOFlags()
17254 FlagSet |= PPC::MOF_SubtargetSPE; in computeMOFlags()
17260 return PPC::MOF_None; in computeMOFlags()
17271 FlagSet |= PPC::MOF_SubWordInt; in computeMOFlags()
17273 FlagSet |= PPC::MOF_WordInt; in computeMOFlags()
17275 FlagSet |= PPC::MOF_DoubleWordInt; in computeMOFlags()
17278 FlagSet |= PPC::MOF_Vector; in computeMOFlags()
17280 FlagSet |= PPC::MOF_Vector256; in computeMOFlags()
17285 FlagSet |= PPC::MOF_ScalarFloat; in computeMOFlags()
17287 FlagSet |= PPC::MOF_Vector; in computeMOFlags()
17299 FlagSet |= PPC::MOF_SExt; in computeMOFlags()
17303 FlagSet |= PPC::MOF_ZExt; in computeMOFlags()
17306 FlagSet |= PPC::MOF_NoExt; in computeMOFlags()
17310 FlagSet |= PPC::MOF_NoExt; in computeMOFlags()
17315 if (MemVT.isScalarInteger() && (FlagSet & PPC::MOF_NoExt)) { in computeMOFlags()
17316 FlagSet |= PPC::MOF_ZExt; in computeMOFlags()
17317 FlagSet &= ~PPC::MOF_NoExt; in computeMOFlags()
17323 ((PPC::MOF_RPlusSImm34 | PPC::MOF_AddrIsSImm32 | PPC::MOF_SubtargetP10) & in computeMOFlags()
17324 FlagSet) == PPC::MOF_RPlusSImm34; in computeMOFlags()
17327 FlagSet |= PPC::MOF_NotAddNorCst; in computeMOFlags()
17334 PPC::AddrMode PPCTargetLowering::SelectForceXFormMode(SDValue N, SDValue &Disp, in SelectForceXFormMode()
17338 PPC::AddrMode Mode = PPC::AM_XForm; in SelectForceXFormMode()
17361 Disp = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectForceXFormMode()
17371 PPC::AddrMode &Mode) { in setXFormForUnalignedFI()
17374 if ((Mode == PPC::AM_DSForm && !(Flags & PPC::MOF_RPlusSImm16Mult4)) || in setXFormForUnalignedFI()
17375 (Mode == PPC::AM_DQForm && !(Flags & PPC::MOF_RPlusSImm16Mult16))) in setXFormForUnalignedFI()
17376 Mode = PPC::AM_XForm; in setXFormForUnalignedFI()
17382 PPC::AddrMode PPCTargetLowering::SelectOptimalAddrMode(const SDNode *Parent, in SelectOptimalAddrMode()
17393 PPC::AddrMode Mode = getAddrModeForFlags(Flags); in SelectOptimalAddrMode()
17401 case PPC::AM_DForm: in SelectOptimalAddrMode()
17402 case PPC::AM_DSForm: in SelectOptimalAddrMode()
17403 case PPC::AM_DQForm: { in SelectOptimalAddrMode()
17407 if (Flags & PPC::MOF_RPlusSImm16) { in SelectOptimalAddrMode()
17423 else if (Flags & PPC::MOF_RPlusLo) { in SelectOptimalAddrMode()
17435 else if (Flags & PPC::MOF_AddrIsSImm32) { in SelectOptimalAddrMode()
17444 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectOptimalAddrMode()
17456 uint32_t LIS = CNType == MVT::i32 ? PPC::LIS : PPC::LIS8; in SelectOptimalAddrMode()
17470 case PPC::AM_None: in SelectOptimalAddrMode()
17476 Disp = FI ? DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectOptimalAddrMode()