Lines Matching refs:Fixups
44 SmallVectorImpl<MCFixup> &Fixups, in getDirectBrEncoding() argument
49 return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
51 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getDirectBrEncoding()
60 SmallVectorImpl<MCFixup> &Fixups, in getCondBrEncoding() argument
63 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
66 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getCondBrEncoding()
73 SmallVectorImpl<MCFixup> &Fixups, in getAbsDirectBrEncoding() argument
76 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
79 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getAbsDirectBrEncoding()
86 SmallVectorImpl<MCFixup> &Fixups, in getAbsCondBrEncoding() argument
89 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
92 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getAbsCondBrEncoding()
99 SmallVectorImpl<MCFixup> &Fixups, in getVSRpEvenEncoding() argument
102 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) in getVSRpEvenEncoding()
108 SmallVectorImpl<MCFixup> &Fixups, in getImm16Encoding() argument
111 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
114 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), in getImm16Encoding()
120 SmallVectorImpl<MCFixup> &Fixups, in getImm34Encoding() argument
126 return getMachineOpValue(MI, MO, Fixups, STI); in getImm34Encoding()
129 Fixups.push_back(MCFixup::create(0, MO.getExpr(), Fixup)); in getImm34Encoding()
135 SmallVectorImpl<MCFixup> &Fixups, in getImm34EncodingNoPCRel() argument
137 return getImm34Encoding(MI, OpNo, Fixups, STI, in getImm34EncodingNoPCRel()
143 SmallVectorImpl<MCFixup> &Fixups, in getImm34EncodingPCRel() argument
145 return getImm34Encoding(MI, OpNo, Fixups, STI, in getImm34EncodingPCRel()
150 SmallVectorImpl<MCFixup> &Fixups, in getMemRIEncoding() argument
155 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; in getMemRIEncoding()
159 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits; in getMemRIEncoding()
162 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), in getMemRIEncoding()
168 SmallVectorImpl<MCFixup> &Fixups, in getMemRIXEncoding() argument
173 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14; in getMemRIXEncoding()
177 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits; in getMemRIXEncoding()
180 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), in getMemRIXEncoding()
186 SmallVectorImpl<MCFixup> &Fixups, in getMemRIX16Encoding() argument
191 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12; in getMemRIX16Encoding()
197 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits; in getMemRIX16Encoding()
201 Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(), in getMemRIX16Encoding()
208 SmallVectorImpl<MCFixup> &Fixups, in getMemRIHashEncoding() argument
219 unsigned RegBits = getMachineOpValue(MI, RegMO, Fixups, STI) << 6; in getMemRIHashEncoding()
226 SmallVectorImpl<MCFixup> &Fixups, in getMemRI34PCRelEncoding() argument
240 getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34; in getMemRI34PCRelEncoding()
247 return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits; in getMemRI34PCRelEncoding()
270 Fixups.push_back( in getMemRI34PCRelEncoding()
304 Fixups.push_back( in getMemRI34PCRelEncoding()
316 SmallVectorImpl<MCFixup> &Fixups, in getMemRI34Encoding() argument
321 uint64_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) in getMemRI34Encoding()
324 return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits; in getMemRI34Encoding()
328 SmallVectorImpl<MCFixup> &Fixups, in getSPE8DisEncoding() argument
334 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; in getSPE8DisEncoding()
338 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3; in getSPE8DisEncoding()
343 SmallVectorImpl<MCFixup> &Fixups, in getSPE4DisEncoding() argument
349 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; in getSPE4DisEncoding()
353 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2; in getSPE4DisEncoding()
358 SmallVectorImpl<MCFixup> &Fixups, in getSPE2DisEncoding() argument
364 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; in getSPE2DisEncoding()
368 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1; in getSPE2DisEncoding()
373 SmallVectorImpl<MCFixup> &Fixups, in getTLSRegEncoding() argument
376 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); in getTLSRegEncoding()
385 Fixups.push_back(MCFixup::create(IsPCRel ? 1 : 0, Expr, in getTLSRegEncoding()
393 SmallVectorImpl<MCFixup> &Fixups, in getTLSCallEncoding() argument
399 Fixups.push_back(MCFixup::create(0, MO.getExpr(), in getTLSCallEncoding()
401 return getDirectBrEncoding(MI, OpNo, Fixups, STI); in getTLSCallEncoding()
406 SmallVectorImpl<MCFixup> &Fixups, in get_crbitm_encoding() argument
431 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue() argument
452 const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction() argument
457 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); in encodeInstruction()