Lines Matching refs:SrcVT
187 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
188 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
191 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
194 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
196 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
997 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPExt() local
1000 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in selectFPExt()
1076 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPTrunc() local
1079 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in selectFPTrunc()
1099 MVT DstVT, SrcVT; in selectFPToInt() local
1112 if (!isTypeLegal(SrcTy, SrcVT)) in selectFPToInt()
1115 if (SrcVT != MVT::f32 && SrcVT != MVT::f64) in selectFPToInt()
1126 unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32; in selectFPToInt()
1210 MVT SrcVT = ArgVT; in processCallArgs() local
1211 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); in processCallArgs()
1218 MVT SrcVT = ArgVT; in processCallArgs() local
1219 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); in processCallArgs()
1782 EVT SrcVT, DestVT; in selectTrunc() local
1783 SrcVT = TLI.getValueType(DL, Op->getType(), true); in selectTrunc()
1786 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in selectTrunc()
1819 MVT SrcVT = SrcEVT.getSimpleVT(); in selectIntExt() local
1823 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt)) in selectIntExt()
1829 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntSExt32r1() argument
1832 switch (SrcVT.SimpleTy) { in emitIntSExt32r1()
1848 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntSExt32r2() argument
1850 switch (SrcVT.SimpleTy) { in emitIntSExt32r2()
1863 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntSExt() argument
1868 return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg); in emitIntSExt()
1869 return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg); in emitIntSExt()
1872 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntZExt() argument
1876 switch (SrcVT.SimpleTy) { in emitIntZExt()
1894 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntExt() argument
1901 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16))) in emitIntExt()
1904 return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg); in emitIntExt()
1905 return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg); in emitIntExt()
1908 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntExt() argument
1911 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt); in emitIntExt()