Lines Matching refs:Mips
304 Opc = Mips::AND; in emitLogicalOp()
307 Opc = Mips::OR; in emitLogicalOp()
310 Opc = Mips::XOR; in emitLogicalOp()
328 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp()
344 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in fastMaterializeAlloca()
345 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu), in fastMaterializeAlloca()
358 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeInt()
368 unsigned Opc = Mips::ADDiu; in materialize32BitInt()
369 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
372 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
380 emitInst(Mips::LUi, TmpReg).addImm(Hi); in materialize32BitInt()
381 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
383 emitInst(Mips::LUi, ResultReg).addImm(Hi); in materialize32BitInt()
393 const TargetRegisterClass *RC = &Mips::FGR32RegClass; in materializeFP()
395 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass); in materializeFP()
396 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
399 const TargetRegisterClass *RC = &Mips::AFGR64RegClass; in materializeFP()
401 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass); in materializeFP()
403 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass); in materializeFP()
404 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); in materializeFP()
414 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeGV()
421 emitInst(Mips::LW, DestReg) in materializeGV()
427 emitInst(Mips::ADDiu, TempReg) in materializeGV()
436 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeExternalCallSym()
438 emitInst(Mips::LW, DestReg) in materializeExternalCallSym()
652 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
653 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
654 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
658 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
659 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
660 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg); in emitCmp()
664 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
667 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
670 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
671 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
672 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
676 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
677 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
678 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
682 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
685 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
688 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
689 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
690 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
694 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
695 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
696 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
714 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32; in emitCmp()
715 CondMovOpc = Mips::MOVT_I; in emitCmp()
718 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32; in emitCmp()
719 CondMovOpc = Mips::MOVF_I; in emitCmp()
722 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32; in emitCmp()
723 CondMovOpc = Mips::MOVT_I; in emitCmp()
726 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32; in emitCmp()
727 CondMovOpc = Mips::MOVT_I; in emitCmp()
730 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32; in emitCmp()
731 CondMovOpc = Mips::MOVF_I; in emitCmp()
734 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32; in emitCmp()
735 CondMovOpc = Mips::MOVF_I; in emitCmp()
740 unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass); in emitCmp()
741 unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass); in emitCmp()
742 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); in emitCmp()
743 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); in emitCmp()
744 emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg) in emitCmp()
748 .addReg(Mips::FCC0) in emitCmp()
764 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
765 Opc = Mips::LW; in emitLoad()
768 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
769 Opc = Mips::LHu; in emitLoad()
772 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
773 Opc = Mips::LBu; in emitLoad()
778 ResultReg = createResultReg(&Mips::FGR32RegClass); in emitLoad()
779 Opc = Mips::LWC1; in emitLoad()
784 ResultReg = createResultReg(&Mips::AFGR64RegClass); in emitLoad()
785 Opc = Mips::LDC1; in emitLoad()
819 Opc = Mips::SB; in emitStore()
822 Opc = Mips::SH; in emitStore()
825 Opc = Mips::SW; in emitStore()
830 Opc = Mips::SWC1; in emitStore()
835 Opc = Mips::SDC1; in emitStore()
959 ZExtCondReg = createResultReg(&Mips::GPR32RegClass); in selectBranch()
976 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ)) in selectBranch()
985 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in selectCmp()
1009 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass); in selectFPExt()
1010 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg); in selectFPExt()
1031 CondMovOpc = Mips::MOVN_I_I; in selectSelect()
1032 RC = &Mips::GPR32RegClass; in selectSelect()
1034 CondMovOpc = Mips::MOVN_I_S; in selectSelect()
1035 RC = &Mips::FGR32RegClass; in selectSelect()
1037 CondMovOpc = Mips::MOVN_I_D32; in selectSelect()
1038 RC = &Mips::AFGR64RegClass; in selectSelect()
1051 unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass); in selectSelect()
1086 unsigned DestReg = createResultReg(&Mips::FGR32RegClass); in selectFPTrunc()
1090 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg); in selectFPTrunc()
1124 unsigned DestReg = createResultReg(&Mips::GPR32RegClass); in selectFPToInt()
1125 unsigned TempReg = createResultReg(&Mips::FGR32RegClass); in selectFPToInt()
1126 unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32; in selectFPToInt()
1130 emitInst(Mips::MFC1, DestReg).addReg(TempReg); in selectFPToInt()
1149 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0); in processCallArgs()
1160 VA.convertToReg(Mips::F12); in processCallArgs()
1163 VA.convertToReg(Mips::D6_64); in processCallArgs()
1165 VA.convertToReg(Mips::D6); in processCallArgs()
1170 VA.convertToReg(Mips::F14); in processCallArgs()
1173 VA.convertToReg(Mips::D7_64); in processCallArgs()
1175 VA.convertToReg(Mips::D7); in processCallArgs()
1184 VA.convertToReg(Mips::A0); in processCallArgs()
1187 VA.convertToReg(Mips::A1); in processCallArgs()
1190 VA.convertToReg(Mips::A2); in processCallArgs()
1193 VA.convertToReg(Mips::A3); in processCallArgs()
1260 Addr.setReg(Mips::SP); in processCallArgs()
1279 emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0); in finishCall()
1331 std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2, in fastLowerArguments()
1332 Mips::A3}}; in fastLowerArguments()
1333 std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}}; in fastLowerArguments()
1334 std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}}; in fastLowerArguments()
1389 Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++); in fastLowerArguments()
1409 Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++); in fastLowerArguments()
1426 Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++); in fastLowerArguments()
1445 Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++); in fastLowerArguments()
1557 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress); in fastLowerCall()
1559 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR), in fastLowerCall()
1560 Mips::RA).addReg(Mips::T9); in fastLowerCall()
1600 unsigned DestReg = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1605 emitInst(Mips::WSBH, DestReg).addReg(SrcReg); in fastLowerIntrinsicCall()
1611 TempReg[i] = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1615 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1616 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1617 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]); in fastLowerIntrinsicCall()
1618 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF); in fastLowerIntrinsicCall()
1624 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1625 emitInst(Mips::WSBH, TempReg).addReg(SrcReg); in fastLowerIntrinsicCall()
1626 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16); in fastLowerIntrinsicCall()
1632 TempReg[i] = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1637 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1638 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24); in fastLowerIntrinsicCall()
1639 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00); in fastLowerIntrinsicCall()
1640 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]); in fastLowerIntrinsicCall()
1642 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00); in fastLowerIntrinsicCall()
1643 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8); in fastLowerIntrinsicCall()
1645 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24); in fastLowerIntrinsicCall()
1646 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]); in fastLowerIntrinsicCall()
1647 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]); in fastLowerIntrinsicCall()
1771 MachineInstrBuilder MIB = emitInst(Mips::RetRA); in selectRet()
1821 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in selectIntExt()
1842 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitIntSExt32r1()
1843 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt); in emitIntSExt32r1()
1844 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt); in emitIntSExt32r1()
1854 emitInst(Mips::SEB, DestReg).addReg(SrcReg); in emitIntSExt32r2()
1857 emitInst(Mips::SEH, DestReg).addReg(SrcReg); in emitIntSExt32r2()
1890 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm); in emitIntZExt()
1910 unsigned DestReg = createResultReg(&Mips::GPR32RegClass); in emitIntExt()
1930 DivOpc = Mips::SDIV; in selectDivRem()
1934 DivOpc = Mips::UDIV; in selectDivRem()
1944 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7); in selectDivRem()
1946 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in selectDivRem()
1951 ? Mips::MFHI in selectDivRem()
1952 : Mips::MFLO; in selectDivRem()
1965 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in selectShift()
1977 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in selectShift()
1996 Opcode = Mips::SLL; in selectShift()
1999 Opcode = Mips::SRA; in selectShift()
2002 Opcode = Mips::SRL; in selectShift()
2019 Opcode = Mips::SLLV; in selectShift()
2022 Opcode = Mips::SRAV; in selectShift()
2025 Opcode = Mips::SRLV; in selectShift()
2103 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in getRegEnsuringSimpleIntegerWidening()
2114 materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass); in simplifyAddress()
2115 unsigned DestReg = createResultReg(&Mips::GPR32RegClass); in simplifyAddress()
2116 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg()); in simplifyAddress()
2131 if (MachineInstOpcode == Mips::MUL) { in fastEmitInst_rr()
2139 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead) in fastEmitInst_rr()
2140 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead); in fastEmitInst_rr()
2149 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo, in createFastISel()