328   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLogicalOp()
344     unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in fastMaterializeAlloca()
358   const TargetRegisterClass *RC = &Mips::GPR32RegClass;  in materializeInt()
395     unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);  in materializeFP()
401     unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);  in materializeFP()
403         materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);  in materializeFP()
414   const TargetRegisterClass *RC = &Mips::GPR32RegClass;  in materializeGV()
436   const TargetRegisterClass *RC = &Mips::GPR32RegClass;  in materializeExternalCallSym()
652     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
658     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
670     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
676     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
688     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
694     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
740     unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
741     unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);  in emitCmp()
764     ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLoad()
768     ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLoad()
772     ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLoad()
959       ZExtCondReg = createResultReg(&Mips::GPR32RegClass);  in selectBranch()
985   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectCmp()
1032     RC = &Mips::GPR32RegClass;  in selectSelect()
1051   unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);  in selectSelect()
1124   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);  in selectFPToInt()
1389       Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);  in fastLowerArguments()
1409       Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);  in fastLowerArguments()
1600     unsigned DestReg = createResultReg(&Mips::GPR32RegClass);  in fastLowerIntrinsicCall()
1611           TempReg[i] = createResultReg(&Mips::GPR32RegClass);  in fastLowerIntrinsicCall()
1624         unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in fastLowerIntrinsicCall()
1632           TempReg[i] = createResultReg(&Mips::GPR32RegClass);  in fastLowerIntrinsicCall()
1821   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectIntExt()
1842   unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in emitIntSExt32r1()
1910   unsigned DestReg = createResultReg(&Mips::GPR32RegClass);  in emitIntExt()
1946   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectDivRem()
1965   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectShift()
1977     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in selectShift()
2103     unsigned TempReg = createResultReg(&Mips::GPR32RegClass);  in getRegEnsuringSimpleIntegerWidening()
2114         materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);  in simplifyAddress()
2115     unsigned DestReg = createResultReg(&Mips::GPR32RegClass);  in simplifyAddress()