Lines Matching refs:RegDefsUses
109 class RegDefsUses { class
111 RegDefsUses(const TargetRegisterInfo &TRI);
255 bool delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
262 RegDefsUses &RegDU, InspectMemInstr &IM, Iter Slot,
290 RegDefsUses &RegDU, bool &HasMultipleSuccs,
344 RegDefsUses::RegDefsUses(const TargetRegisterInfo &TRI) in RegDefsUses() function in RegDefsUses
347 void RegDefsUses::init(const MachineInstr &MI) { in init()
364 void RegDefsUses::setCallerSaved(const MachineInstr &MI) { in setCallerSaved()
389 void RegDefsUses::setUnallocatableRegs(const MachineFunction &MF) { in setUnallocatableRegs()
402 void RegDefsUses::addLiveOut(const MachineBasicBlock &MBB, in addLiveOut()
411 bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) { in update()
434 bool RegDefsUses::checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, in checkRegDefsUses()
447 bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const { in isRegInSet()
693 IterTy End, RegDefsUses &RegDU, in searchRange()
780 RegDefsUses RegDU(*Fn->getSubtarget().getRegisterInfo()); in searchBackward()
806 RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo()); in searchForward()
834 RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo()); in searchSuccBBs()
926 RegDefsUses &RegDU, in examinePred()
948 RegDefsUses &RegDU, in delayHasHazard()