Lines Matching refs:Fixups
154 SmallVectorImpl<MCFixup> &Fixups, in encodeInstruction() argument
182 unsigned long N = Fixups.size(); in encodeInstruction()
183 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in encodeInstruction()
208 if (Fixups.size() > N) in encodeInstruction()
209 Fixups.pop_back(); in encodeInstruction()
212 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); in encodeInstruction()
217 unsigned RegPair = getMovePRegPairOpValue(MI, 0, Fixups, STI); in encodeInstruction()
237 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValue() argument
249 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTargetOpValue()
259 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValue1SImm16() argument
271 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTargetOpValue1SImm16()
281 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValueMMR6() argument
294 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTargetOpValueMMR6()
304 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValueLsl2MMR6() argument
317 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTargetOpValueLsl2MMR6()
327 SmallVectorImpl<MCFixup> &Fixups, in getBranchTarget7OpValueMM() argument
338 Fixups.push_back(MCFixup::create(0, Expr, in getBranchTarget7OpValueMM()
348 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValueMMPC10() argument
359 Fixups.push_back(MCFixup::create(0, Expr, in getBranchTargetOpValueMMPC10()
369 SmallVectorImpl<MCFixup> &Fixups, in getBranchTargetOpValueMM() argument
380 Fixups.push_back(MCFixup::create(0, Expr, in getBranchTargetOpValueMM()
391 SmallVectorImpl<MCFixup> &Fixups, in getBranchTarget21OpValue() argument
403 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTarget21OpValue()
413 SmallVectorImpl<MCFixup> &Fixups, in getBranchTarget21OpValueMM() argument
425 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTarget21OpValueMM()
435 SmallVectorImpl<MCFixup> &Fixups, in getBranchTarget26OpValue() argument
447 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTarget26OpValue()
456 const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, in getBranchTarget26OpValueMM() argument
469 Fixups.push_back(MCFixup::create(0, FixupExpression, in getBranchTarget26OpValueMM()
479 SmallVectorImpl<MCFixup> &Fixups, in getJumpOffset16OpValue() argument
489 Mips::Fixups FixupKind = in getJumpOffset16OpValue()
491 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind))); in getJumpOffset16OpValue()
500 SmallVectorImpl<MCFixup> &Fixups, in getJumpTargetOpValue() argument
510 Fixups.push_back(MCFixup::create(0, Expr, in getJumpTargetOpValue()
517 SmallVectorImpl<MCFixup> &Fixups, in getJumpTargetOpValueMM() argument
527 Fixups.push_back(MCFixup::create(0, Expr, in getJumpTargetOpValueMM()
534 SmallVectorImpl<MCFixup> &Fixups, in getUImm5Lsl2Encoding() argument
539 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); in getUImm5Lsl2Encoding()
552 SmallVectorImpl<MCFixup> &Fixups, in getSImm3Lsa2Value() argument
565 SmallVectorImpl<MCFixup> &Fixups, in getUImm6Lsl2Encoding() argument
578 SmallVectorImpl<MCFixup> &Fixups, in getSImm9AddiuspValue() argument
590 getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, in getExprOpValue() argument
604 getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI); in getExprOpValue()
605 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI); in getExprOpValue()
612 Mips::Fixups FixupKind = Mips::Fixups(0); in getExprOpValue()
621 return getExprOpValue(MipsExpr->getSubExpr(), Fixups, STI); in getExprOpValue()
722 Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind))); in getExprOpValue()
735 SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue() argument
748 return getExprOpValue(MO.getExpr(),Fixups, STI); in getMachineOpValue()
755 SmallVectorImpl<MCFixup> &Fixups, in getMemEncoding() argument
759 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) in getMemEncoding()
761 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncoding()
771 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm4() argument
776 Fixups, STI) << 4; in getMemEncodingMMImm4()
778 Fixups, STI); in getMemEncodingMMImm4()
785 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm4Lsl1() argument
790 Fixups, STI) << 4; in getMemEncodingMMImm4Lsl1()
792 Fixups, STI) >> 1; in getMemEncodingMMImm4Lsl1()
799 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm4Lsl2() argument
804 Fixups, STI) << 4; in getMemEncodingMMImm4Lsl2()
806 Fixups, STI) >> 2; in getMemEncodingMMImm4Lsl2()
813 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMSPImm5Lsl2() argument
821 Fixups, STI) >> 2; in getMemEncodingMMSPImm5Lsl2()
828 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMGPImm7Lsl2() argument
836 Fixups, STI) >> 2; in getMemEncodingMMGPImm7Lsl2()
843 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm9() argument
847 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, in getMemEncodingMMImm9()
850 getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI); in getMemEncodingMMImm9()
857 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm11() argument
861 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, in getMemEncodingMMImm11()
863 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncodingMMImm11()
870 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm12() argument
885 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) in getMemEncodingMMImm12()
887 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncodingMMImm12()
894 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm16() argument
898 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, in getMemEncodingMMImm16()
900 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncodingMMImm16()
907 SmallVectorImpl<MCFixup> &Fixups, in getMemEncodingMMImm4sp() argument
926 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncodingMMImm4sp()
935 SmallVectorImpl<MCFixup> &Fixups, in getSizeInsEncoding() argument
939 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI); in getSizeInsEncoding()
940 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); in getSizeInsEncoding()
948 SmallVectorImpl<MCFixup> &Fixups, in getUImmWithOffsetEncoding() argument
951 unsigned Value = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); in getUImmWithOffsetEncoding()
958 SmallVectorImpl<MCFixup> &Fixups, in getSimm19Lsl2Encoding() argument
963 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); in getSimm19Lsl2Encoding()
972 Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC19_S2 in getSimm19Lsl2Encoding()
974 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind))); in getSimm19Lsl2Encoding()
980 SmallVectorImpl<MCFixup> &Fixups, in getSimm18Lsl3Encoding() argument
985 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); in getSimm18Lsl3Encoding()
994 Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC18_S3 in getSimm18Lsl3Encoding()
996 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind))); in getSimm18Lsl3Encoding()
1002 SmallVectorImpl<MCFixup> &Fixups, in getUImm3Mod8Encoding() argument
1011 SmallVectorImpl<MCFixup> &Fixups, in getUImm4AndValue() argument
1039 SmallVectorImpl<MCFixup> &Fixups, in getRegisterListOpValue() argument
1059 SmallVectorImpl<MCFixup> &Fixups, in getRegisterListOpValue16() argument
1066 SmallVectorImpl<MCFixup> &Fixups, in getMovePRegPairOpValue() argument
1100 SmallVectorImpl<MCFixup> &Fixups, in getMovePRegSingleOpValue() argument
1123 SmallVectorImpl<MCFixup> &Fixups, in getSimm23Lsl2Encoding() argument