Lines Matching refs:Decoder
85 const void *Decoder);
90 const void *Decoder);
95 const void *Decoder);
100 const void *Decoder);
105 const void *Decoder);
110 const void *Decoder);
115 const void *Decoder);
120 const void *Decoder);
125 const void *Decoder);
130 const void *Decoder);
135 const void *Decoder);
140 const void *Decoder);
144 const void *Decoder);
149 const void *Decoder);
154 const void *Decoder);
159 const void *Decoder);
164 const void *Decoder);
169 const void *Decoder);
174 const void *Decoder);
179 const void *Decoder);
184 const void *Decoder);
189 const void *Decoder);
194 const void *Decoder);
199 const void *Decoder);
204 const void *Decoder);
209 const void *Decoder);
214 const void *Decoder);
219 const void *Decoder);
224 const void *Decoder);
229 const void *Decoder);
234 const void *Decoder);
241 const void *Decoder);
248 const void *Decoder);
255 const void *Decoder);
262 const void *Decoder);
269 const void *Decoder);
276 const void *Decoder);
281 const void *Decoder);
286 const void *Decoder);
291 const void *Decoder);
294 const void *Decoder);
299 const void *Decoder);
304 const void *Decoder);
309 const void *Decoder);
314 const void *Decoder);
319 const void *Decoder);
324 const void *Decoder);
327 uint64_t Address, const void *Decoder);
332 const void *Decoder);
337 const void *Decoder);
342 const void *Decoder);
347 const void *Decoder);
352 const void *Decoder);
357 const void *Decoder);
362 const void *Decoder);
366 const void *Decoder);
370 const void *Decoder);
373 const void *Decoder);
376 const void *Decoder);
379 uint64_t Address, const void *Decoder);
383 const void *Decoder);
388 const void *Decoder);
393 const void *Decoder);
398 const void *Decoder);
403 const void *Decoder);
408 const void *Decoder);
413 const void *Decoder) { in DecodeUImmWithOffset() argument
415 Decoder); in DecodeUImmWithOffset()
421 const void *Decoder);
426 const void *Decoder);
429 uint64_t Address, const void *Decoder);
432 uint64_t Address, const void *Decoder);
435 uint64_t Address, const void *Decoder);
438 uint64_t Address, const void *Decoder);
441 uint64_t Address, const void *Decoder);
447 const void *Decoder);
451 uint64_t Address, const void *Decoder);
455 const void *Decoder);
459 uint64_t Address, const void *Decoder);
463 const void *Decoder);
468 const void *Decoder);
473 const void *Decoder);
478 const void *Decoder);
483 const void *Decoder);
488 const void *Decoder);
493 const void *Decoder);
498 const void *Decoder);
503 const void *Decoder);
508 const void *Decoder);
513 const void *Decoder);
518 const void *Decoder);
523 const void *Decoder);
527 const void *Decoder);
531 const void *Decoder);
535 const void *Decoder);
539 const void *Decoder);
543 const void *Decoder);
547 const void *Decoder);
550 uint64_t Address, const void *Decoder);
588 const void *Decoder) { in DecodeINSVE_DF() argument
615 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) in DecodeINSVE_DF()
618 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) in DecodeINSVE_DF()
625 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) in DecodeINSVE_DF()
635 uint64_t Address, const void *Decoder) { in DecodeDAHIDATIMMR6() argument
638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
640 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
649 const void *Decoder) { in DecodeDAHIDATI() argument
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
654 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
664 const void *Decoder) { in DecodeAddiGroupBranch() argument
690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
693 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
703 const void *Decoder) { in DecodePOP35GroupBranchMMR6() argument
710 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
712 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
717 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
719 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
724 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
737 const void *Decoder) { in DecodeDaddiGroupBranch() argument
763 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
766 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
776 const void *Decoder) { in DecodePOP37GroupBranchMMR6() argument
783 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
785 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
790 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
792 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
797 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
810 const void *Decoder) { in DecodePOP65GroupBranchMMR6() argument
835 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP65GroupBranchMMR6()
838 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP65GroupBranchMMR6()
849 const void *Decoder) { in DecodePOP75GroupBranchMMR6() argument
874 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP75GroupBranchMMR6()
877 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP75GroupBranchMMR6()
888 const void *Decoder) { in DecodeBlezlGroupBranch() argument
917 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
920 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
931 const void *Decoder) { in DecodeBgtzlGroupBranch() argument
961 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzlGroupBranch()
964 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzlGroupBranch()
975 const void *Decoder) { in DecodeBgtzGroupBranch() argument
1009 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzGroupBranch()
1013 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzGroupBranch()
1024 const void *Decoder) { in DecodeBlezGroupBranch() argument
1053 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezGroupBranch()
1055 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezGroupBranch()
1067 const void *Decoder) { in DecodeDEXT() argument
1096 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); in DecodeDEXT()
1098 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); in DecodeDEXT()
1109 const void *Decoder) { in DecodeDINS() argument
1139 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); in DecodeDINS()
1141 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); in DecodeDINS()
1151 const void *Decoder) { in DecodeCRC() argument
1154 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeCRC()
1156 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeCRC()
1158 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeCRC()
1398 const void *Decoder) { in DecodeCPU16RegsRegisterClass() argument
1405 const void *Decoder) { in DecodeGPR64RegisterClass() argument
1409 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); in DecodeGPR64RegisterClass()
1417 const void *Decoder) { in DecodeGPRMM16RegisterClass() argument
1420 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); in DecodeGPRMM16RegisterClass()
1428 const void *Decoder) { in DecodeGPRMM16ZeroRegisterClass() argument
1431 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); in DecodeGPRMM16ZeroRegisterClass()
1439 const void *Decoder) { in DecodeGPRMM16MovePRegisterClass() argument
1442 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); in DecodeGPRMM16MovePRegisterClass()
1450 const void *Decoder) { in DecodeGPR32RegisterClass() argument
1453 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); in DecodeGPR32RegisterClass()
1461 const void *Decoder) { in DecodePtrRegisterClass() argument
1462 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) in DecodePtrRegisterClass()
1463 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); in DecodePtrRegisterClass()
1465 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); in DecodePtrRegisterClass()
1471 const void *Decoder) { in DecodeDSPRRegisterClass() argument
1472 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); in DecodeDSPRRegisterClass()
1478 const void *Decoder) { in DecodeFGR64RegisterClass() argument
1482 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); in DecodeFGR64RegisterClass()
1490 const void *Decoder) { in DecodeFGR32RegisterClass() argument
1494 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); in DecodeFGR32RegisterClass()
1502 const void *Decoder) { in DecodeCCRRegisterClass() argument
1505 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); in DecodeCCRRegisterClass()
1513 const void *Decoder) { in DecodeFCCRegisterClass() argument
1516 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); in DecodeFCCRegisterClass()
1523 const void *Decoder) { in DecodeFGRCCRegisterClass() argument
1527 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); in DecodeFGRCCRegisterClass()
1535 const void *Decoder) { in DecodeMem() argument
1540 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMem()
1541 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMem()
1557 const void *Decoder) { in DecodeMemEVA() argument
1562 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemEVA()
1563 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMemEVA()
1578 const void *Decoder) { in DecodeLoadByte15() argument
1583 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeLoadByte15()
1584 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeLoadByte15()
1596 const void *Decoder) { in DecodeCacheOp() argument
1601 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeCacheOp()
1613 const void *Decoder) { in DecodeCacheOpMM() argument
1618 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeCacheOpMM()
1630 const void *Decoder) { in DecodePrefeOpMM() argument
1635 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodePrefeOpMM()
1647 const void *Decoder) { in DecodeCacheeOp_CacheOpR6() argument
1652 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeCacheeOp_CacheOpR6()
1664 const void *Decoder) { in DecodeSyncI() argument
1668 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeSyncI()
1677 uint64_t Address, const void *Decoder) { in DecodeSyncI_MM() argument
1681 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeSyncI_MM()
1692 const void *Decoder) { in DecodeSynciR6() argument
1696 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeSynciR6()
1705 uint64_t Address, const void *Decoder) { in DecodeMSA128Mem() argument
1710 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); in DecodeMSA128Mem()
1711 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMSA128Mem()
1753 const void *Decoder) { in DecodeMemMMImm4() argument
1762 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) in DecodeMemMMImm4()
1772 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) in DecodeMemMMImm4()
1778 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) in DecodeMemMMImm4()
1811 const void *Decoder) { in DecodeMemMMSPImm5Lsl2() argument
1815 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMSPImm5Lsl2()
1827 const void *Decoder) { in DecodeMemMMGPImm7Lsl2() argument
1831 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMGPImm7Lsl2()
1843 const void *Decoder) { in DecodeMemMMReglistImm4Lsl2() argument
1855 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) in DecodeMemMMReglistImm4Lsl2()
1868 const void *Decoder) { in DecodeMemMMImm9() argument
1873 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMImm9()
1874 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMemMMImm9()
1889 const void *Decoder) { in DecodeMemMMImm12() argument
1894 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMImm12()
1895 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMemMMImm12()
1900 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) in DecodeMemMMImm12()
1924 const void *Decoder) { in DecodeMemMMImm16() argument
1929 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMImm16()
1930 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMemMMImm16()
1942 const void *Decoder) { in DecodeFMem() argument
1947 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); in DecodeFMem()
1948 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMem()
1958 uint64_t Address, const void *Decoder) { in DecodeFMemMMR2() argument
1965 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); in DecodeFMemMMR2()
1966 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMemMMR2()
1978 const void *Decoder) { in DecodeFMem2() argument
1983 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); in DecodeFMem2()
1984 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMem2()
1996 const void *Decoder) { in DecodeFMem3() argument
2001 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); in DecodeFMem3()
2002 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMem3()
2014 const void *Decoder) { in DecodeFMemCop2R6() argument
2019 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); in DecodeFMemCop2R6()
2020 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMemCop2R6()
2030 uint64_t Address, const void *Decoder) { in DecodeFMemCop2MMR6() argument
2035 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); in DecodeFMemCop2MMR6()
2036 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMemCop2MMR6()
2048 const void *Decoder) { in DecodeSpecial3LlSc() argument
2053 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); in DecodeSpecial3LlSc()
2054 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeSpecial3LlSc()
2070 const void *Decoder) { in DecodeHWRegsRegisterClass() argument
2081 const void *Decoder) { in DecodeAFGR64RegisterClass() argument
2085 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); in DecodeAFGR64RegisterClass()
2093 const void *Decoder) { in DecodeACC64DSPRegisterClass() argument
2097 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); in DecodeACC64DSPRegisterClass()
2105 const void *Decoder) { in DecodeHI32DSPRegisterClass() argument
2109 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); in DecodeHI32DSPRegisterClass()
2117 const void *Decoder) { in DecodeLO32DSPRegisterClass() argument
2121 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); in DecodeLO32DSPRegisterClass()
2129 const void *Decoder) { in DecodeMSA128BRegisterClass() argument
2133 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); in DecodeMSA128BRegisterClass()
2141 const void *Decoder) { in DecodeMSA128HRegisterClass() argument
2145 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); in DecodeMSA128HRegisterClass()
2153 const void *Decoder) { in DecodeMSA128WRegisterClass() argument
2157 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); in DecodeMSA128WRegisterClass()
2165 const void *Decoder) { in DecodeMSA128DRegisterClass() argument
2169 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); in DecodeMSA128DRegisterClass()
2177 const void *Decoder) { in DecodeMSACtrlRegisterClass() argument
2181 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); in DecodeMSACtrlRegisterClass()
2189 const void *Decoder) { in DecodeCOP0RegisterClass() argument
2193 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); in DecodeCOP0RegisterClass()
2201 const void *Decoder) { in DecodeCOP2RegisterClass() argument
2205 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); in DecodeCOP2RegisterClass()
2213 const void *Decoder) { in DecodeBranchTarget() argument
2222 const void *Decoder) { in DecodeBranchTarget1SImm16() argument
2231 const void *Decoder) { in DecodeJumpTarget() argument
2240 const void *Decoder) { in DecodeBranchTarget21() argument
2250 const void *Decoder) { in DecodeBranchTarget21MM() argument
2260 const void *Decoder) { in DecodeBranchTarget26() argument
2270 const void *Decoder) { in DecodeBranchTarget7MM() argument
2279 const void *Decoder) { in DecodeBranchTarget10MM() argument
2288 const void *Decoder) { in DecodeBranchTargetMM() argument
2297 const void *Decoder) { in DecodeBranchTarget26MM() argument
2307 const void *Decoder) { in DecodeJumpTargetMM() argument
2316 const void *Decoder) { in DecodeJumpTargetXMM() argument
2325 const void *Decoder) { in DecodeAddiur2Simm7() argument
2338 const void *Decoder) { in DecodeLi16Imm() argument
2349 const void *Decoder) { in DecodePOOL16BEncodedField() argument
2357 const void *Decoder) { in DecodeUImmWithOffsetAndScale() argument
2367 const void *Decoder) { in DecodeSImmWithOffsetAndScale() argument
2376 const void *Decoder) { in DecodeInsSize() argument
2387 uint64_t Address, const void *Decoder) { in DecodeSimm19Lsl2() argument
2393 uint64_t Address, const void *Decoder) { in DecodeSimm18Lsl3() argument
2399 uint64_t Address, const void *Decoder) { in DecodeSimm9SP() argument
2413 uint64_t Address, const void *Decoder) { in DecodeANDI16Imm() argument
2425 const void *Decoder) { in DecodeRegListOperand() argument
2453 const void *Decoder) { in DecodeRegListOperand16() argument
2477 const void *Decoder) { in DecodeMovePOperands() argument
2479 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) == in DecodeMovePOperands()
2484 if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6()) in DecodeMovePOperands()
2489 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == in DecodeMovePOperands()
2494 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == in DecodeMovePOperands()
2502 uint64_t Address, const void *Decoder) { in DecodeMovePRegPair() argument
2544 uint64_t Address, const void *Decoder) { in DecodeSimm23Lsl2() argument
2552 const void *Decoder) { in DecodeBgtzGroupBranchMMR6() argument
2587 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); in DecodeBgtzGroupBranchMMR6()
2591 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); in DecodeBgtzGroupBranchMMR6()
2601 const void *Decoder) { in DecodeBlezGroupBranchMMR6() argument
2632 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); in DecodeBlezGroupBranchMMR6()
2634 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); in DecodeBlezGroupBranchMMR6()