Lines Matching refs:Sub
410 if (RR.Sub == 0) { in getSubregMask()
422 if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi) in getSubregMask()
902 if (RR.Sub == 0) in getFinalVRegClass()
907 auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void { in getFinalVRegClass() argument
909 assert(Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_lo) || in getFinalVRegClass()
910 Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_hi)); in getFinalVRegClass()
915 VerifySR(RC, RR.Sub); in getFinalVRegClass()
918 VerifySR(RC, RR.Sub); in getFinalVRegClass()
1350 .addReg(RS.Reg, 0, RS.Sub); in processBlock()
1351 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in processBlock()
1569 Out.Sub = 0; in findMatch()
1581 Out.Sub = Hexagon::isub_lo; in findMatch()
1583 Out.Sub = Hexagon::isub_hi; in findMatch()
1622 .addReg(MR.Reg, 0, MR.Sub); in processBlock()
1641 .addReg(ML.Reg, 0, ML.Sub) in processBlock()
1643 .addReg(MH.Reg, 0, MH.Sub) in processBlock()
1687 if (RS.Sub != 0) in propagateRegCopy()
1688 Changed = HBS::replaceRegWithSub(RD.Reg, RS.Reg, RS.Sub, MRI); in propagateRegCopy()
1699 Changed = HBS::replaceSubWithSub(RD.Reg, SubLo, SL.Reg, SL.Sub, MRI); in propagateRegCopy()
1700 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy()
1710 Changed = HBS::replaceSubWithSub(RD.Reg, SubLo, RL.Reg, RL.Sub, MRI); in propagateRegCopy()
1711 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, RH.Reg, RH.Sub, MRI); in propagateRegCopy()
1717 unsigned Sub = (Opc == Hexagon::A4_combineir) ? Hexagon::isub_lo in propagateRegCopy() local
1720 Changed = HBS::replaceSubWithSub(RD.Reg, Sub, RS.Reg, RS.Sub, MRI); in propagateRegCopy()
1852 unsigned Sub = 0; in matchHalf() local
1855 Sub = Hexagon::isub_lo; in matchHalf()
1859 Sub = Hexagon::isub_lo; in matchHalf()
1863 Sub = Hexagon::isub_hi; in matchHalf()
1867 Sub = Hexagon::isub_hi; in matchHalf()
1875 RH.Sub = Sub; in matchHalf()
1879 RH.Sub = 0; in matchHalf()
1904 if (H1.Reg != L1.Reg || H1.Sub != L1.Sub || H1.Low || !L1.Low) in matchPackhl()
1906 if (H2.Reg != L2.Reg || H2.Sub != L2.Sub || H2.Low || !L2.Low) in matchPackhl()
1941 ValOp.setSubReg(H.Sub); in genStoreUpperHalf()
2041 .addReg(Rs.Reg, 0, Rs.Sub) in genPackhl()
2042 .addReg(Rt.Reg, 0, Rt.Sub); in genPackhl()
2043 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genPackhl()
2070 .addReg(L.Reg, 0, L.Sub); in genExtractHalf()
2076 .addReg(L.Reg, 0, L.Sub) in genExtractHalf()
2082 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genExtractHalf()
2096 if (L.Reg == H.Reg && L.Sub == H.Sub && !H.Low && L.Low) in genCombineHalf()
2112 .addReg(H.Reg, 0, H.Sub) in genCombineHalf()
2113 .addReg(L.Reg, 0, L.Sub); in genCombineHalf()
2114 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genCombineHalf()
2169 .addReg(RS.Reg, 0, RS.Sub); in genExtractLow()
2174 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genExtractLow()
2361 RR.Sub = Hexagon::isub_lo; in simplifyTstbit()
2364 RR.Sub = Hexagon::isub_hi; in simplifyTstbit()
2372 .addReg(RR.Reg, 0, RR.Sub) in simplifyTstbit()
2416 assert(RD.Sub == 0); in simplifyExtractLow()
2470 dbgs() << __func__ << " on reg: " << printReg(RD.Reg, &HRI, RD.Sub) in simplifyExtractLow()
2598 assert(RD.Sub == 0); in simplifyRCmp0()
2673 if (SR.Sub == 0 && InpDef->getOpcode() == Hexagon::C2_muxii) { in simplifyRCmp0()
3145 << printReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber() in processLoop()
3146 << ',' << printReg(I.LR.Reg, HRI, I.LR.Sub) << ":b" in processLoop()
3266 << printReg(G.Inp.Reg, HRI, G.Inp.Sub) in processLoop()
3267 << " out: " << printReg(G.Out.Reg, HRI, G.Out.Sub) << "\n"; in processLoop()