Lines Matching refs:RegisterCell

203     static bool isEqual(const BitTracker::RegisterCell &RC1, uint16_t B1,
204 const BitTracker::RegisterCell &RC2, uint16_t B2, uint16_t W);
205 static bool isZero(const BitTracker::RegisterCell &RC, uint16_t B,
207 static bool getConst(const BitTracker::RegisterCell &RC, uint16_t B,
314 bool HexagonBitSimplify::isEqual(const BitTracker::RegisterCell &RC1, in isEqual()
315 uint16_t B1, const BitTracker::RegisterCell &RC2, uint16_t B2, in isEqual()
330 bool HexagonBitSimplify::isZero(const BitTracker::RegisterCell &RC, in isZero()
339 bool HexagonBitSimplify::getConst(const BitTracker::RegisterCell &RC, in getConst()
1280 const BitTracker::RegisterCell &DC = BT.lookup(RD.Reg); in usedBitsEqual()
1281 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in usedBitsEqual()
1323 const BitTracker::RegisterCell &DC = BT.lookup(RD.Reg); in processBlock()
1340 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in processBlock()
1484 const BitTracker::RegisterCell &DRC = BT.lookup(DR); in processBlock()
1550 const BitTracker::RegisterCell &InpRC = BT.lookup(Inp.Reg); in findMatch()
1559 const BitTracker::RegisterCell &RC = BT.lookup(R); in findMatch()
1763 bool matchHalf(unsigned SelfR, const BitTracker::RegisterCell &RC,
1767 bool matchPackhl(unsigned SelfR, const BitTracker::RegisterCell &RC,
1774 const BitTracker::RegisterCell &RC);
1776 const BitTracker::RegisterCell &RC);
1778 const BitTracker::RegisterCell &RC);
1780 const BitTracker::RegisterCell &RC);
1782 const BitTracker::RegisterCell &RC, const RegisterSet &AVs);
1784 const BitTracker::RegisterCell &RC);
1786 const BitTracker::RegisterCell &RC, const RegisterSet &AVs);
1807 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) { in matchHalf()
1835 const BitTracker::RegisterCell &SC = BT.lookup(Reg); in matchHalf()
1894 const BitTracker::RegisterCell &RC, BitTracker::RegisterRef &Rs, in matchPackhl()
1933 const BitTracker::RegisterCell &RC = BT.lookup(RS.Reg); in genStoreUpperHalf()
1978 const BitTracker::RegisterCell &RC = BT.lookup(RS.Reg); in genStoreImmediate()
2024 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in genPackhl()
2051 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in genExtractHalf()
2090 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in genCombineHalf()
2122 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in genExtractLow()
2156 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in genExtractLow()
2182 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC, in genBitSplit()
2202 auto ctlz = [] (const BitTracker::RegisterCell &C) -> unsigned { in genBitSplit()
2243 const BitTracker::RegisterCell &SC = BT.lookup(S); in genBitSplit()
2335 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in simplifyTstbit()
2350 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in simplifyTstbit()
2395 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC, in simplifyExtractLow()
2482 const BitTracker::RegisterCell &SC = BT.lookup(R); in simplifyExtractLow()
2610 const BitTracker::RegisterCell &SC = BT.lookup(SR.Reg); in simplifyRCmp0()
2628 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0()
2696 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0()
2740 const BitTracker::RegisterCell &RC = BT.lookup(RD.Reg); in processBlock()
2980 const BitTracker::RegisterCell &RC = BTP->lookup(Reg); in isConst()
3034 const BitTracker::RegisterCell &OutC = BTP->lookup(OutR); in isShuffleOf()
3049 const BitTracker::RegisterCell &OutC1 = BTP->lookup(OutR1); in isSameShuffle()
3050 const BitTracker::RegisterCell &OutC2 = BTP->lookup(OutR2); in isSameShuffle()