Lines Matching refs:RegVT
1159 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
1161 if (RegVT == MVT::i8) { in LowerFormalArguments()
1163 } else if (RegVT == MVT::i16) { in LowerFormalArguments()
1170 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
1187 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
1192 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
1291 EVT RegVT = VA.getLocVT(); in LowerCall() local
1301 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1304 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
1307 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
1310 Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg); in LowerCall()