862     ARM_AM::ShiftOpc ShiftTy;  member
872     ARM_AM::ShiftOpc ShiftTy;  member
879     ARM_AM::ShiftOpc ShiftTy;  member
1449     return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;  in isPostIdxReg()
2551       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));  in addRegShiftedRegOperands()
2562       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));  in addRegShiftedImmOperands()
3305                                      PostIdxReg.ShiftTy);  in addPostIdxRegShiftedOperands()
3643     Op->RegShiftedReg.ShiftTy = ShTy;  in CreateShiftedRegister()
3656     Op->RegShiftedImm.ShiftTy = ShTy;  in CreateShiftedImmediate()
3821   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,  in CreatePostIdxReg()  argument
3826     Op->PostIdxReg.ShiftTy = ShiftTy;  in CreatePostIdxReg()
3964     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)  in print()
3965       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "  in print()
3987        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "  in print()
3992        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"  in print()
4141   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)  in tryParseShiftRegister()  local
4150   if (ShiftTy == ARM_AM::no_shift)  in tryParseShiftRegister()
4167   if (ShiftTy == ARM_AM::rrx) {  in tryParseShiftRegister()
4194           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||  in tryParseShiftRegister()
4195           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {  in tryParseShiftRegister()
4202         ShiftTy = ARM_AM::lsl;  in tryParseShiftRegister()
4218   if (ShiftReg && ShiftTy != ARM_AM::rrx)  in tryParseShiftRegister()
4219     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,  in tryParseShiftRegister()
4223     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,  in tryParseShiftRegister()
5645   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;  in parsePostIdxReg()  local
5649     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))  in parsePostIdxReg()
5656   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,  in parsePostIdxReg()
10095     ARM_AM::ShiftOpc ShiftTy;  in processInstruction()  local
10098     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;  in processInstruction()
10099     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;  in processInstruction()
10100     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;  in processInstruction()
10101     case ARM::RORr: ShiftTy = ARM_AM::ror; break;  in processInstruction()
10103     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);  in processInstruction()
10120     ARM_AM::ShiftOpc ShiftTy;  in processInstruction()  local
10123     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;  in processInstruction()
10124     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;  in processInstruction()
10125     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;  in processInstruction()
10126     case ARM::RORi: ShiftTy = ARM_AM::ror; break;  in processInstruction()
10132     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))  in processInstruction()
10134     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);  in processInstruction()