Lines Matching refs:ShiftReg
874 unsigned ShiftReg; member
1389 RegShiftedReg.ShiftReg); in isRegShiftedReg()
2549 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
3640 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, in CreateShiftedRegister() argument
3645 Op->RegShiftedReg.ShiftReg = ShiftReg; in CreateShiftedRegister()
3988 << RegName(RegShiftedReg.ShiftReg) << ">"; in print()
4166 int ShiftReg = 0; in tryParseShiftRegister() local
4171 ShiftReg = SrcReg; in tryParseShiftRegister()
4206 ShiftReg = tryParseRegister(); in tryParseShiftRegister()
4207 if (ShiftReg == -1) { in tryParseShiftRegister()
4218 if (ShiftReg && ShiftTy != ARM_AM::rrx) in tryParseShiftRegister()
4220 ShiftReg, Imm, in tryParseShiftRegister()