826     unsigned RegNum;  member
831     unsigned RegNum;  member
860     unsigned RegNum;  member
966     return Reg.RegNum;  in getReg()
1446            ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum);  in isPostIdxRegShifted()
2029                VectorList.RegNum);  in isVecListTwoMQ()
2035               .contains(VectorList.RegNum));  in isVecListDPair()
2052               .contains(VectorList.RegNum));  in isVecListDPairSpaced()
2068                VectorList.RegNum);  in isVecListFourMQ()
2087               .contains(VectorList.RegNum));  in isVecListDPairAllLanes()
2476     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;  in addCondCodeOperands()  local
2477     Inst.addOperand(MCOperand::createReg(RegNum));  in addCondCodeOperands()
2483     unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0;  in addVPTPredNOperands()  local
2484     Inst.addOperand(MCOperand::createReg(RegNum));  in addVPTPredNOperands()
2490     unsigned RegNum;  in addVPTPredROperands()  local
2492       RegNum = 0;  in addVPTPredROperands()
2499       RegNum = Inst.getOperand(TiedOp).getReg();  in addVPTPredROperands()
2501     Inst.addOperand(MCOperand::createReg(RegNum));  in addVPTPredROperands()
3029       Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));  in addAM3OffsetOperands()
3294     Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));  in addPostIdxRegOperands()
3300     Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));  in addPostIdxRegShiftedOperands()
3332     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));  in addVecListOperands()
3359       if (RC_in->getRegister(I) == VectorList.RegNum)  in addMVEVecListOperands()
3368     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));  in addVecListIndexedOperands()
3612   static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {  in CreateCCOut()  argument
3614     Op->Reg.RegNum = RegNum;  in CreateCCOut()
3629   static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,  in CreateReg()  argument
3632     Op->Reg.RegNum = RegNum;  in CreateReg()
3746   static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,  in CreateVectorList()  argument
3751     Op->VectorList.RegNum = RegNum;  in CreateVectorList()
3760   CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,  in CreateVectorListAllLanes()  argument
3763     Op->VectorList.RegNum = RegNum;  in CreateVectorListAllLanes()
3772   CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,  in CreateVectorListIndexed()  argument
3775     Op->VectorList.RegNum = RegNum;  in CreateVectorListIndexed()
3821   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,  in CreatePostIdxReg()  argument
3824     Op->PostIdxReg.RegNum = RegNum;  in CreatePostIdxReg()
3963        << RegName(PostIdxReg.RegNum);  in print()
4029        << RegName(VectorList.RegNum) << ">";  in print()
4033        << RegName(VectorList.RegNum) << ">";  in print()
4037        << VectorList.Count << " * " << RegName(VectorList.RegNum) << ">";  in print()
4082   unsigned RegNum = MatchRegisterName(lowerCase);  in tryParseRegister()  local
4083   if (!RegNum) {  in tryParseRegister()
4084     RegNum = StringSwitch<unsigned>(lowerCase)  in tryParseRegister()
4107   if (!RegNum) {  in tryParseRegister()
4120   if (!hasD32() && RegNum >= ARM::D16 && RegNum <= ARM::D31)  in tryParseRegister()
4125   return RegNum;  in tryParseRegister()