Lines Matching refs:Operands
447 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
449 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
505 OperandVector &Operands);
506 bool CDEConvertDualRegOperand(StringRef Mnemonic, OperandVector &Operands);
649 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
650 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
651 bool shouldOmitVectorPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
653 void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands);
654 bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
698 SMLoc NameLoc, OperandVector &Operands) override;
706 OperandVector &Operands, MCStreamer &Out,
709 unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
723 SMLoc IDLoc, OperandVector &Operands);
725 OperandVector &Operands);
4133 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { in tryParseShiftRegister() argument
4159 (ARMOperand *)Operands.pop_back_val().release()); in tryParseShiftRegister()
4219 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, in tryParseShiftRegister()
4223 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, in tryParseShiftRegister()
4235 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) { in tryParseRegisterWithWriteBack() argument
4243 Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc)); in tryParseRegisterWithWriteBack()
4247 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), in tryParseRegisterWithWriteBack()
4273 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), in tryParseRegisterWithWriteBack()
4332 ARMAsmParser::parseITCondCode(OperandVector &Operands) { in parseITCondCode() argument
4343 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); in parseITCondCode()
4352 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) { in parseCoprocNumOperand() argument
4366 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); in parseCoprocNumOperand()
4374 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) { in parseCoprocRegOperand() argument
4386 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); in parseCoprocRegOperand()
4393 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) { in parseCoprocOptionOperand() argument
4421 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); in parseCoprocOptionOperand()
4466 bool ARMAsmParser::parseRegisterList(OperandVector &Operands, in parseRegisterList() argument
4614 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); in parseRegisterList()
4618 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); in parseRegisterList()
4679 ARMAsmParser::parseVectorList(OperandVector &Operands) { in parseVectorList() argument
4698 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); in parseVectorList()
4701 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, in parseVectorList()
4705 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, in parseVectorList()
4721 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); in parseVectorList()
4726 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, in parseVectorList()
4730 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, in parseVectorList()
4921 Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E)); in parseVectorList()
4925 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, in parseVectorList()
4936 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) { in parseMemBarrierOptOperand() argument
5002 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); in parseMemBarrierOptOperand()
5007 ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) { in parseTraceSyncBarrierOptOperand() argument
5020 Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S)); in parseTraceSyncBarrierOptOperand()
5026 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) { in parseInstSyncBarrierOptOperand() argument
5070 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( in parseInstSyncBarrierOptOperand()
5078 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) { in parseProcIFlagsOperand() argument
5107 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); in parseProcIFlagsOperand()
5113 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { in parseMSRMaskOperand() argument
5125 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S)); in parseMSRMaskOperand()
5141 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S)); in parseMSRMaskOperand()
5204 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); in parseMSRMaskOperand()
5211 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) { in parseBankedRegOperand() argument
5225 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S)); in parseBankedRegOperand()
5230 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low, in parsePKHImm() argument
5273 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); in parsePKHImm()
5279 ARMAsmParser::parseSetEndImm(OperandVector &Operands) { in parseSetEndImm() argument
5297 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val, in parseSetEndImm()
5309 ARMAsmParser::parseShifterImm(OperandVector &Operands) { in parseShifterImm() argument
5371 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); in parseShifterImm()
5380 ARMAsmParser::parseRotImm(OperandVector &Operands) { in parseRotImm() argument
5421 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); in parseRotImm()
5427 ARMAsmParser::parseModImm(OperandVector &Operands) { in parseModImm() argument
5474 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF), in parseModImm()
5487 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); in parseModImm()
5493 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); in parseModImm()
5532 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2)); in parseModImm()
5544 ARMAsmParser::parseBitfield(OperandVector &Operands) { in parseBitfield() argument
5607 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); in parseBitfield()
5613 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) { in parsePostIdxReg() argument
5656 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, in parsePostIdxReg()
5663 ARMAsmParser::parseAM3Offset(OperandVector &Operands) { in parseAM3Offset() argument
5701 Operands.push_back( in parseAM3Offset()
5727 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, in parseAM3Offset()
5737 const OperandVector &Operands) { in cvtThumbMultiply() argument
5738 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); in cvtThumbMultiply()
5739 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1); in cvtThumbMultiply()
5743 if (Operands.size() == 6 && in cvtThumbMultiply()
5744 ((ARMOperand &)*Operands[4]).getReg() == in cvtThumbMultiply()
5745 ((ARMOperand &)*Operands[3]).getReg()) in cvtThumbMultiply()
5747 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); in cvtThumbMultiply()
5749 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2); in cvtThumbMultiply()
5753 const OperandVector &Operands) { in cvtThumbBranches() argument
5776 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode(); in cvtThumbBranches()
5793 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); in cvtThumbBranches()
5800 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); in cvtThumbBranches()
5806 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1); in cvtThumbBranches()
5807 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2); in cvtThumbBranches()
5811 MCInst &Inst, const OperandVector &Operands) { in cvtMVEVMOVQtoDReg() argument
5814 assert(Operands.size() == 8); in cvtMVEVMOVQtoDReg()
5816 ((ARMOperand &)*Operands[2]).addRegOperands(Inst, 1); // Rt in cvtMVEVMOVQtoDReg()
5817 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2 in cvtMVEVMOVQtoDReg()
5818 ((ARMOperand &)*Operands[4]).addRegOperands(Inst, 1); // Qd in cvtMVEVMOVQtoDReg()
5819 ((ARMOperand &)*Operands[5]).addMVEPairVectorIndexOperands(Inst, 1); // idx in cvtMVEVMOVQtoDReg()
5821 ((ARMOperand &)*Operands[7]).addMVEPairVectorIndexOperands(Inst, 1); // idx2 in cvtMVEVMOVQtoDReg()
5822 ((ARMOperand &)*Operands[1]).addCondCodeOperands(Inst, 2); // condition code in cvtMVEVMOVQtoDReg()
5827 bool ARMAsmParser::parseMemory(OperandVector &Operands) { in parseMemory() argument
5850 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, in parseMemory()
5857 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
5907 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, in parseMemory()
5914 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
5950 Operands.push_back(ARMOperand::CreateMem( in parseMemory()
5962 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
5999 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum, in parseMemory()
6006 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
6081 ARMAsmParser::parseFPImm(OperandVector &Operands) { in parseFPImm() argument
6108 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]); in parseFPImm()
6112 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]); in parseFPImm()
6134 Operands.push_back(ARMOperand::CreateImm( in parseFPImm()
6151 Operands.push_back(ARMOperand::CreateImm( in parseFPImm()
6163 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { in parseOperand() argument
6169 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); in parseOperand()
6188 if (!tryParseRegisterWithWriteBack(Operands)) in parseOperand()
6190 int Res = tryParseShiftRegister(Operands); in parseOperand()
6200 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); in parseOperand()
6220 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); in parseOperand()
6224 return parseMemory(Operands); in parseOperand()
6226 return parseRegisterList(Operands, !Mnemonic.startswith("clr")); in parseOperand()
6261 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); in parseOperand()
6267 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), in parseOperand()
6292 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); in parseOperand()
6307 Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E)); in parseOperand()
6619 OperandVector &Operands) { in tryConvertingToTwoOperandForm() argument
6620 if (Operands.size() != 6) in tryConvertingToTwoOperandForm()
6623 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]); in tryConvertingToTwoOperandForm()
6624 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]); in tryConvertingToTwoOperandForm()
6635 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]); in tryConvertingToTwoOperandForm()
6695 Operands.erase(Operands.begin() + 3); in tryConvertingToTwoOperandForm()
6700 OperandVector &Operands) { in shouldOmitCCOutOperand() argument
6712 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && in shouldOmitCCOutOperand()
6713 !static_cast<ARMOperand &>(*Operands[4]).isModImm() && in shouldOmitCCOutOperand()
6714 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() && in shouldOmitCCOutOperand()
6715 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) in shouldOmitCCOutOperand()
6720 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && in shouldOmitCCOutOperand()
6721 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6722 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
6723 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) in shouldOmitCCOutOperand()
6731 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6732 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
6733 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
6734 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
6735 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) || in shouldOmitCCOutOperand()
6736 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4())) in shouldOmitCCOutOperand()
6744 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6745 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
6746 static_cast<ARMOperand &>(*Operands[5]).isImm()) { in shouldOmitCCOutOperand()
6752 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) && in shouldOmitCCOutOperand()
6753 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) && in shouldOmitCCOutOperand()
6754 static_cast<ARMOperand &>(*Operands[5]).isImm0_7()) in shouldOmitCCOutOperand()
6758 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC && in shouldOmitCCOutOperand()
6759 (static_cast<ARMOperand &>(*Operands[5]).isT2SOImm() || in shouldOmitCCOutOperand()
6760 static_cast<ARMOperand &>(*Operands[5]).isT2SOImmNeg())) in shouldOmitCCOutOperand()
6771 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && in shouldOmitCCOutOperand()
6772 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
6773 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6774 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
6775 static_cast<ARMOperand &>(*Operands[5]).isReg() && in shouldOmitCCOutOperand()
6780 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || in shouldOmitCCOutOperand()
6781 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || in shouldOmitCCOutOperand()
6782 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) || in shouldOmitCCOutOperand()
6783 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() != in shouldOmitCCOutOperand()
6784 static_cast<ARMOperand &>(*Operands[5]).getReg() && in shouldOmitCCOutOperand()
6785 static_cast<ARMOperand &>(*Operands[3]).getReg() != in shouldOmitCCOutOperand()
6786 static_cast<ARMOperand &>(*Operands[4]).getReg()))) in shouldOmitCCOutOperand()
6791 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && in shouldOmitCCOutOperand()
6792 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
6793 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6794 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
6798 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || in shouldOmitCCOutOperand()
6799 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || in shouldOmitCCOutOperand()
6809 (Operands.size() == 5 || Operands.size() == 6) && in shouldOmitCCOutOperand()
6810 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6811 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
6812 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
6813 (static_cast<ARMOperand &>(*Operands[4]).isImm() || in shouldOmitCCOutOperand()
6814 (Operands.size() == 6 && in shouldOmitCCOutOperand()
6815 static_cast<ARMOperand &>(*Operands[5]).isImm()))) { in shouldOmitCCOutOperand()
6818 (static_cast<ARMOperand &>(*Operands[4]).isT2SOImm() || in shouldOmitCCOutOperand()
6819 static_cast<ARMOperand &>(*Operands[4]).isT2SOImmNeg()))); in shouldOmitCCOutOperand()
6825 (Operands.size() == 5) && in shouldOmitCCOutOperand()
6826 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6827 static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::SP && in shouldOmitCCOutOperand()
6828 static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::PC && in shouldOmitCCOutOperand()
6829 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
6830 static_cast<ARMOperand &>(*Operands[4]).isImm()) { in shouldOmitCCOutOperand()
6831 const ARMOperand &IMM = static_cast<ARMOperand &>(*Operands[4]); in shouldOmitCCOutOperand()
6838 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg())) in shouldOmitCCOutOperand()
6847 OperandVector &Operands) { in shouldOmitPredicateOperand() argument
6852 (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" || in shouldOmitPredicateOperand()
6853 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) { in shouldOmitPredicateOperand()
6854 if (static_cast<ARMOperand &>(*Operands[3]).isToken() && in shouldOmitPredicateOperand()
6855 (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" || in shouldOmitPredicateOperand()
6856 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16")) in shouldOmitPredicateOperand()
6859 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() && in shouldOmitPredicateOperand()
6861 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || in shouldOmitPredicateOperand()
6863 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()))) in shouldOmitPredicateOperand()
6870 OperandVector &Operands) { in shouldOmitVectorPredicateOperand() argument
6871 if (!hasMVE() || Operands.size() < 3) in shouldOmitVectorPredicateOperand()
6884 for (auto &Operand : Operands) { in shouldOmitVectorPredicateOperand()
6896 for (auto &Operand : Operands) { in shouldOmitVectorPredicateOperand()
6939 OperandVector &Operands) { in fixupGNULDRDAlias() argument
6942 if (Operands.size() < 4) in fixupGNULDRDAlias()
6945 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]); in fixupGNULDRDAlias()
6946 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); in fixupGNULDRDAlias()
6970 Operands.insert( in fixupGNULDRDAlias()
6971 Operands.begin() + 3, in fixupGNULDRDAlias()
6981 OperandVector &Operands) { in CDEConvertDualRegOperand() argument
6987 if (Operands.size() <= 3 + NumPredOps) in CDEConvertDualRegOperand()
6993 const MCParsedAsmOperand &Op2 = *Operands[2 + NumPredOps]; in CDEConvertDualRegOperand()
7028 const MCParsedAsmOperand &Op3 = *Operands[3 + NumPredOps]; in CDEConvertDualRegOperand()
7032 Operands.erase(Operands.begin() + 3 + NumPredOps); in CDEConvertDualRegOperand()
7033 Operands[2 + NumPredOps] = in CDEConvertDualRegOperand()
7040 SMLoc NameLoc, OperandVector &Operands) { in ParseInstruction() argument
7080 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); in ParseInstruction()
7113 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); in ParseInstruction()
7153 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, in ParseInstruction()
7161 Operands.push_back(ARMOperand::CreateCondCode( in ParseInstruction()
7178 Operands.push_back(ARMOperand::CreateVPTPred( in ParseInstruction()
7184 Operands.push_back(ARMOperand::CreateImm( in ParseInstruction()
7215 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); in ParseInstruction()
7222 if (parseOperand(Operands, Mnemonic)) { in ParseInstruction()
7228 if (parseOperand(Operands, Mnemonic)) { in ParseInstruction()
7237 tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands); in ParseInstruction()
7248 bool GotError = CDEConvertDualRegOperand(Mnemonic, Operands); in ParseInstruction()
7261 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) in ParseInstruction()
7262 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7269 shouldOmitPredicateOperand(Mnemonic, Operands)) in ParseInstruction()
7270 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7274 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands) && in ParseInstruction()
7279 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7280 Operands.erase(Operands.begin()); in ParseInstruction()
7284 Operands.insert(Operands.begin(), in ParseInstruction()
7286 Operands.insert(Operands.begin(), in ParseInstruction()
7289 !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { in ParseInstruction()
7294 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7295 Operands.erase(Operands.begin()); in ParseInstruction()
7299 Operands.insert(Operands.begin(), in ParseInstruction()
7301 Operands.insert(Operands.begin(), in ParseInstruction()
7304 !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { in ParseInstruction()
7308 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7309 Operands.erase(Operands.begin()); in ParseInstruction()
7311 Operands.insert(Operands.begin(), in ParseInstruction()
7323 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { in ParseInstruction()
7330 if (Mnemonic.startswith("vcvtt") && Operands.size() >= 4) { in ParseInstruction()
7331 auto Sz1 = static_cast<ARMOperand &>(*Operands[2]); in ParseInstruction()
7332 auto Sz2 = static_cast<ARMOperand &>(*Operands[3]); in ParseInstruction()
7335 Operands.erase(Operands.begin()); in ParseInstruction()
7340 Operands.insert(Operands.begin(), in ParseInstruction()
7344 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7347 Operands.insert(Operands.begin() + 1, in ParseInstruction()
7355 if (shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { in ParseInstruction()
7357 Operands.erase(Operands.begin() + 2); in ParseInstruction()
7359 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7361 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7368 for (unsigned I = 1; I < Operands.size(); ++I) in ParseInstruction()
7369 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred()) in ParseInstruction()
7380 Operands.erase(Operands.begin()); in ParseInstruction()
7381 Operands.insert(Operands.begin(), in ParseInstruction()
7391 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && in ParseInstruction()
7392 static_cast<ARMOperand &>(*Operands[2]).isImm()) in ParseInstruction()
7393 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7402 if (!isThumb() && Operands.size() > 4 && in ParseInstruction()
7407 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]); in ParseInstruction()
7408 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]); in ParseInstruction()
7427 Operands[Idx] = in ParseInstruction()
7429 Operands.erase(Operands.begin() + Idx + 1); in ParseInstruction()
7434 fixupGNULDRDAlias(Mnemonic, Operands); in ParseInstruction()
7441 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 && in ParseInstruction()
7442 static_cast<ARMOperand &>(*Operands[3]).isReg() && in ParseInstruction()
7443 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC && in ParseInstruction()
7444 static_cast<ARMOperand &>(*Operands[4]).isReg() && in ParseInstruction()
7445 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR && in ParseInstruction()
7446 static_cast<ARMOperand &>(*Operands[5]).isImm()) { in ParseInstruction()
7447 Operands.front() = ARMOperand::CreateToken(Name, NameLoc); in ParseInstruction()
7448 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7494 const OperandVector &Operands, in validatetLDMRegList() argument
7496 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); in validatetLDMRegList()
7504 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetLDMRegList()
7507 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetLDMRegList()
7513 const OperandVector &Operands, in validatetSTMRegList() argument
7515 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); in validatetSTMRegList()
7522 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetSTMRegList()
7525 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetSTMRegList()
7528 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetSTMRegList()
7534 const OperandVector &Operands, in validateLDRDSTRD() argument
7543 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7548 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7554 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7557 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7567 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7576 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7580 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7605 const OperandVector &Operands) { in validateInstruction() argument
7607 SMLoc Loc = Operands[0]->getStartLoc(); in validateInstruction()
7621 for (unsigned I = 1; I < Operands.size(); ++I) in validateInstruction()
7622 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode()) in validateInstruction()
7623 CondLoc = Operands[I]->getStartLoc(); in validateInstruction()
7668 for (unsigned I = 1; I < Operands.size(); ++I) in validateInstruction()
7669 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred()) in validateInstruction()
7670 PredLoc = Operands[I]->getStartLoc(); in validateInstruction()
7699 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true, in validateInstruction()
7705 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true, in validateInstruction()
7710 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false, in validateInstruction()
7716 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false, in validateInstruction()
7724 return Error(Operands[2]->getStartLoc(), in validateInstruction()
7729 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true, in validateInstruction()
7735 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true, in validateInstruction()
7741 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/false, in validateInstruction()
7766 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7779 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7785 return Error(Operands[5]->getStartLoc(), in validateInstruction()
7791 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7826 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7870 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7886 return Error(Operands[5]->getStartLoc(), in validateInstruction()
7900 (static_cast<ARMOperand &>(*Operands[3]).isToken() && in validateInstruction()
7901 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); in validateInstruction()
7904 return Error(Operands[3 + HasWritebackToken]->getStartLoc(), in validateInstruction()
7908 return Error(Operands[2]->getStartLoc(), in validateInstruction()
7913 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7917 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
7930 return Error(Operands.back()->getStartLoc(), in validateInstruction()
7935 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
7940 if (validatetSTMRegList(Inst, Operands, 3)) in validateInstruction()
7948 return Error(Operands.back()->getStartLoc(), in validateInstruction()
7952 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
7955 if (validatetSTMRegList(Inst, Operands, 3)) in validateInstruction()
7965 return Error(Operands[4]->getStartLoc(), in validateInstruction()
7973 return Error(Operands[2]->getStartLoc(), in validateInstruction()
7984 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() != in validateInstruction()
7985 ((ARMOperand &)*Operands[5]).getReg()) && in validateInstruction()
7986 (((ARMOperand &)*Operands[3]).getReg() != in validateInstruction()
7987 ((ARMOperand &)*Operands[4]).getReg())) { in validateInstruction()
7988 return Error(Operands[3]->getStartLoc(), in validateInstruction()
8000 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8002 if (validatetLDMRegList(Inst, Operands, 2, !isMClass())) in validateInstruction()
8010 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8012 if (validatetSTMRegList(Inst, Operands, 2)) in validateInstruction()
8021 return Error(Operands[4]->getStartLoc(), in validateInstruction()
8027 return Error(Operands[4]->getStartLoc(), in validateInstruction()
8031 if (validatetSTMRegList(Inst, Operands, 4)) in validateInstruction()
8040 return Error(Operands[4]->getStartLoc(), in validateInstruction()
8051 return Error(Operands[4]->getStartLoc(), in validateInstruction()
8057 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>()) in validateInstruction()
8058 return Error(Operands[2]->getStartLoc(), "branch target out of range"); in validateInstruction()
8061 int op = (Operands[2]->isImm()) ? 2 : 3; in validateInstruction()
8062 ARMOperand &Operand = static_cast<ARMOperand &>(*Operands[op]); in validateInstruction()
8066 return Error(Operands[op]->getStartLoc(), "branch target out of range"); in validateInstruction()
8071 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>()) in validateInstruction()
8072 return Error(Operands[2]->getStartLoc(), "branch target out of range"); in validateInstruction()
8075 int Op = (Operands[2]->isImm()) ? 2 : 3; in validateInstruction()
8076 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>()) in validateInstruction()
8077 return Error(Operands[Op]->getStartLoc(), "branch target out of range"); in validateInstruction()
8082 if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<6, 1>()) in validateInstruction()
8083 return Error(Operands[2]->getStartLoc(), "branch target out of range"); in validateInstruction()
8097 int i = (Operands[3]->isImm()) ? 3 : 4; in validateInstruction()
8098 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]); in validateInstruction()
8118 return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not " in validateInstruction()
8122 return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not " in validateInstruction()
8131 if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<4, 1>() || in validateInstruction()
8133 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8137 if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<16, 1>()) in validateInstruction()
8138 return Error(Operands[3]->getStartLoc(), in validateInstruction()
8141 if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<18, 1>()) in validateInstruction()
8142 return Error(Operands[3]->getStartLoc(), in validateInstruction()
8148 if (!static_cast<ARMOperand &>(*Operands[1]).isUnsignedOffset<4, 1>() || in validateInstruction()
8150 return Error(Operands[1]->getStartLoc(), in validateInstruction()
8153 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<16, 1>()) in validateInstruction()
8154 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8165 Operands[3]->getStartLoc(), in validateInstruction()
8175 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8193 return Error(Operands[1]->getStartLoc(), in validateInstruction()
8197 return Error(Operands[1]->getStartLoc(), in validateInstruction()
8207 return Error(Operands[5]->getStartLoc(), in validateInstruction()
8216 return Error(Operands[3]->getStartLoc(), in validateInstruction()
8222 ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]); in validateInstruction()
8225 return Error(Operands[3]->getStartLoc(), in validateInstruction()
8236 if (Operands[3]->getReg() == Operands[4]->getReg()) { in validateInstruction()
8237 return Error (Operands[3]->getStartLoc(), in validateInstruction()
8240 if (Operands[3]->getReg() == Operands[5]->getReg()) { in validateInstruction()
8241 return Error (Operands[3]->getStartLoc(), in validateInstruction()
8247 if (Operands[4]->getReg() != Operands[6]->getReg()) in validateInstruction()
8248 return Error (Operands[4]->getStartLoc(), "Q-registers must be the same"); in validateInstruction()
8249 if (static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() != in validateInstruction()
8250 static_cast<ARMOperand &>(*Operands[7]).getVectorIndex() + 2) in validateInstruction()
8251 return Error (Operands[5]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1"); in validateInstruction()
8255 if (Operands[2]->getReg() != Operands[4]->getReg()) in validateInstruction()
8256 return Error (Operands[2]->getStartLoc(), "Q-registers must be the same"); in validateInstruction()
8257 if (static_cast<ARMOperand &>(*Operands[3]).getVectorIndex() != in validateInstruction()
8258 static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() + 2) in validateInstruction()
8259 return Error (Operands[3]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1"); in validateInstruction()
8331 return Error(Operands[1]->getStartLoc(), in validateInstruction()
8334 return Error(Operands[1]->getStartLoc(), in validateInstruction()
8394 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8660 const OperandVector &Operands, in processInstruction() argument
8665 for (auto &Op : Operands) { in processInstruction()
8832 static_cast<ARMOperand &>(*Operands[4]) : in processInstruction()
8833 static_cast<ARMOperand &>(*Operands[3])); in processInstruction()
10195 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" && in processInstruction()
10213 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" && in processInstruction()
10232 const StringRef Token = static_cast<ARMOperand &>(*Operands[0]).getToken(); in processInstruction()
10259 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { in processInstruction()
10269 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { in processInstruction()
10389 (static_cast<ARMOperand &>(*Operands[3]).isToken() && in processInstruction()
10390 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); in processInstruction()
10832 unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst, in MatchInstruction() argument
10839 return MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm); in MatchInstruction()
10845 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) == in MatchInstruction()
10871 MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm); in MatchInstruction()
10898 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) == in MatchInstruction()
10922 OperandVector &Operands, in MatchAndEmitInstruction() argument
10930 MatchResult = MatchInstruction(Operands, Inst, NearMisses, MatchingInlineAsm, in MatchAndEmitInstruction()
10941 if (validateInstruction(Inst, Operands)) { in MatchAndEmitInstruction()
10956 while (processInstruction(Inst, Operands, Out)) in MatchAndEmitInstruction()
10989 ReportNearMisses(NearMisses, IDLoc, Operands); in MatchAndEmitInstruction()
10994 ((ARMOperand &)*Operands[0]).getToken(), FBS); in MatchAndEmitInstruction()
10996 ((ARMOperand &)*Operands[0]).getLocRange()); in MatchAndEmitInstruction()
11680 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; in parseDirectiveRegSave() local
11683 if (parseRegisterList(Operands) || in parseDirectiveRegSave()
11686 ARMOperand &Op = (ARMOperand &)*Operands[0]; in parseDirectiveRegSave()
12061 SMLoc IDLoc, OperandVector &Operands) { in FilterNearMisses() argument
12084 ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc(); in FilterNearMisses()
12198 SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc(); in FilterNearMisses()
12214 SMLoc IDLoc, OperandVector &Operands) { in ReportNearMisses() argument
12216 FilterNearMisses(NearMisses, Messages, IDLoc, Operands); in ReportNearMisses()