176         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
182         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
219   unsigned Opcode = MI.getOpcode();  in getMemoryOpOffset()  local
220   bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;  in getMemoryOpOffset()
224   if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||  in getMemoryOpOffset()
225       Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 ||  in getMemoryOpOffset()
226       Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 ||  in getMemoryOpOffset()
227       Opcode == ARM::LDRi12   || Opcode == ARM::STRi12)  in getMemoryOpOffset()
231   if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi ||  in getMemoryOpOffset()
232       Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi)  in getMemoryOpOffset()
254 static int getLoadStoreMultipleOpcode(unsigned Opcode, ARM_AM::AMSubMode Mode) {  in getLoadStoreMultipleOpcode()  argument
255   switch (Opcode) {  in getLoadStoreMultipleOpcode()
339 static ARM_AM::AMSubMode getLoadStoreMultipleSubMode(unsigned Opcode) {  in getLoadStoreMultipleSubMode()  argument
340   switch (Opcode) {  in getLoadStoreMultipleSubMode()
627     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,  in CreateLoadStoreMulti()  argument
647     if (Opcode == ARM::tLDRi)  in CreateLoadStoreMulti()
649     else if (Opcode == ARM::tSTRi)  in CreateLoadStoreMulti()
655   bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);  in CreateLoadStoreMulti()
665   } else if (Offset != 0 || Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {  in CreateLoadStoreMulti()
668     if (!getLoadStoreMultipleOpcode(Opcode, Mode)) return nullptr;  in CreateLoadStoreMulti()
682     if (isi32Load(Opcode)) {  in CreateLoadStoreMulti()
692       if (!isLoadSingle(Opcode))  in CreateLoadStoreMulti()
727       (!isi32Store(Opcode) || !ContainsReg(Regs, Base));  in CreateLoadStoreMulti()
777   bool isDef = isLoadSingle(Opcode);  in CreateLoadStoreMulti()
781   Opcode = getLoadStoreMultipleOpcode(Opcode, Mode);  in CreateLoadStoreMulti()
782   if (!Opcode)  in CreateLoadStoreMulti()
800     if (Opcode == ARM::tLDMIA) {  in CreateLoadStoreMulti()
803       Opcode = ARM::tLDMIA_UPD;  in CreateLoadStoreMulti()
806     MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));  in CreateLoadStoreMulti()
818     MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));  in CreateLoadStoreMulti()
834     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,  in CreateLoadStoreDouble()  argument
838   bool IsLoad = isi32Load(Opcode);  in CreateLoadStoreDouble()
839   assert((IsLoad || isi32Store(Opcode)) && "Must have integer load or store");  in CreateLoadStoreDouble()
860   unsigned Opcode = First->getOpcode();  in MergeOpsUpdate()  local
861   bool IsLoad = isLoadSingle(Opcode);  in MergeOpsUpdate()
911                                    Opcode, Pred, PredReg, DL, Regs,  in MergeOpsUpdate()
915                                   Opcode, Pred, PredReg, DL, Regs, Cand.Instrs);  in MergeOpsUpdate()
940   if (isLoadSingle(Opcode)) {  in MergeOpsUpdate()
961     assert(isi32Store(Opcode) || Opcode == ARM::VSTRS || Opcode == ARM::VSTRD);  in MergeOpsUpdate()
989   unsigned Opcode = MI.getOpcode();  in mayCombineMisaligned()  local
990   if (!isi32Load(Opcode) && !isi32Store(Opcode))  in mayCombineMisaligned()
1004   unsigned Opcode = FirstMI->getOpcode();  in FormCandidates()  local
1005   bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);  in FormCandidates()
1025     if (STI->isCortexM3() && isi32Load(Opcode) &&  in FormCandidates()
1046     switch (Opcode) {  in FormCandidates()
1296   unsigned Opcode = MI->getOpcode();  in MergeBaseUpdateLSMultiple()  local
1311   ARM_AM::AMSubMode Mode = getLoadStoreMultipleSubMode(Opcode);  in MergeBaseUpdateLSMultiple()
1346   unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);  in MergeBaseUpdateLSMultiple()
1474   unsigned Opcode = MI->getOpcode();  in MergeBaseUpdateLoadStore()  local
1476   bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS ||  in MergeBaseUpdateLoadStore()
1477                 Opcode == ARM::VSTRD || Opcode == ARM::VSTRS);  in MergeBaseUpdateLoadStore()
1478   bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STRi12);  in MergeBaseUpdateLoadStore()
1479   if (isi32Load(Opcode) || isi32Store(Opcode))  in MergeBaseUpdateLoadStore()
1500     NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add);  in MergeBaseUpdateLoadStore()
1502     NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);  in MergeBaseUpdateLoadStore()
1508     NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add);  in MergeBaseUpdateLoadStore()
1511       NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);  in MergeBaseUpdateLoadStore()
1521   bool isLd = isLoadSingle(Opcode);  in MergeBaseUpdateLoadStore()
1612   unsigned Opcode = MI.getOpcode();  in MergeBaseUpdateLSDouble()  local
1613   assert((Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) &&  in MergeBaseUpdateLSDouble()
1637     NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_PRE : ARM::t2STRD_PRE;  in MergeBaseUpdateLSDouble()
1642     NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_POST : ARM::t2STRD_POST;  in MergeBaseUpdateLSDouble()
1659   assert(TII->get(Opcode).getNumOperands() == 6 &&  in MergeBaseUpdateLSDouble()
1676   unsigned Opcode = MI.getOpcode();  in isMemoryOp()  local
1677   switch (Opcode) {  in isMemoryOp()
1761   unsigned Opcode = MI->getOpcode();  in FixInvalidRegPairOp()  local
1764   if (Opcode != ARM::LDRD && Opcode != ARM::STRD && Opcode != ARM::t2LDRDi8)  in FixInvalidRegPairOp()
1777     (Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8) && STI->isCortexM3();  in FixInvalidRegPairOp()
1779   bool NonConsecutiveRegs = (Opcode == ARM::LDRD || Opcode == ARM::STRD) &&  in FixInvalidRegPairOp()
1785   bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8;  in FixInvalidRegPairOp()
1786   bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;  in FixInvalidRegPairOp()
1894       unsigned Opcode = MBBI->getOpcode();  in LoadStoreMultipleOpti()  local
1904         CurrOpc  = Opcode;  in LoadStoreMultipleOpti()
1910       if (CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred) {  in LoadStoreMultipleOpti()
1919         if (isLoadSingle(Opcode)) {  in LoadStoreMultipleOpti()
1998         unsigned Opcode = Merged->getOpcode();  in LoadStoreMultipleOpti()  local
1999         if (Opcode == ARM::t2STRDi8 || Opcode == ARM::t2LDRDi8)  in LoadStoreMultipleOpti()
2049     unsigned Opcode = PrevMI.getOpcode();  in MergeReturnIntoLDM()  local
2050     if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::LDMDA_UPD ||  in MergeReturnIntoLDM()
2051         Opcode == ARM::LDMDB_UPD || Opcode == ARM::LDMIB_UPD ||  in MergeReturnIntoLDM()
2052         Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {  in MergeReturnIntoLDM()
2057       assert(((isThumb2 && Opcode == ARM::t2LDMIA_UPD) ||  in MergeReturnIntoLDM()
2058               Opcode == ARM::LDMIA_UPD) && "Unsupported multiple load-return!");  in MergeReturnIntoLDM()
2266   unsigned Opcode = Op0->getOpcode();  in CanFormLdStDWord()  local
2267   if (Opcode == ARM::LDRi12) {  in CanFormLdStDWord()
2269   } else if (Opcode == ARM::STRi12) {  in CanFormLdStDWord()
2271   } else if (Opcode == ARM::t2LDRi8 || Opcode == ARM::t2LDRi12) {  in CanFormLdStDWord()
2275   } else if (Opcode == ARM::t2STRi8 || Opcode == ARM::t2STRi12) {  in CanFormLdStDWord()
2708 static bool isLegalOrConvertableAddressImm(unsigned Opcode, int Imm,  in isLegalOrConvertableAddressImm()  argument
2711   if (isLegalAddressImm(Opcode, Imm, TII))  in isLegalOrConvertableAddressImm()
2715   const MCInstrDesc &Desc = TII->get(Opcode);  in isLegalOrConvertableAddressImm()