173                            ARMCC::CondCodes Pred, unsigned PredReg);
177         ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
183         ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
487                                         ARMCC::CondCodes Pred,  in UpdateBaseRegUses()
628     ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,  in CreateLoadStoreMulti()
835     ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,  in CreateLoadStoreDouble()
906   ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg);  in MergeOpsUpdate()
1189                                   ARMCC::CondCodes Pred, Register PredReg) {  in isIncrementOrDecrement()
1221                  ARMCC::CondCodes Pred, Register PredReg, int &Offset) {  in findIncDecBefore()
1241                 ARMCC::CondCodes Pred, Register PredReg, int &Offset,  in findIncDecAfter()
1295   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in MergeBaseUpdateLSMultiple()
1491   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in MergeBaseUpdateLoadStore()
1629   ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);  in MergeBaseUpdateLSDouble()
1734                           bool BaseKill, bool BaseUndef, ARMCC::CondCodes Pred,  in InsertLDR_STR()
1799   ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);  in FixInvalidRegPairOp()
1879   ARMCC::CondCodes CurrPred = ARMCC::AL;  in LoadStoreMultipleOpti()
1899       ARMCC::CondCodes Pred = getInstrPredicate(*MBBI, PredReg);  in LoadStoreMultipleOpti()
2174                           ARMCC::CondCodes &Pred, bool &isT2);
2259     Register &PredReg, ARMCC::CondCodes &Pred, bool &isT2) {  in CanFormLdStDWord()
2423         ARMCC::CondCodes Pred = ARMCC::AL;  in RescheduleOps()