176         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
182         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
627     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,  in CreateLoadStoreMulti()  argument
701     int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm  in CreateLoadStoreMulti()
713       BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm  in CreateLoadStoreMulti()
726     bool KillOldBase = BaseKill &&  in CreateLoadStoreMulti()
774     BaseKill = true; // New base is always killed straight away.  in CreateLoadStoreMulti()
793   if (isThumb1 && !SafeToClobberCPSR && Writeback && !BaseKill)  in CreateLoadStoreMulti()
810        .addReg(Base, getKillRegState(BaseKill));  in CreateLoadStoreMulti()
814     if (!BaseKill)  in CreateLoadStoreMulti()
819     MIB.addReg(Base, getKillRegState(BaseKill));  in CreateLoadStoreMulti()
834     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,  in CreateLoadStoreDouble()  argument
904   bool BaseKill = LatestMI->killsRegister(Base);  in MergeOpsUpdate()  local
910     Merged = CreateLoadStoreDouble(MBB, InsertBefore, Offset, Base, BaseKill,  in MergeOpsUpdate()
914     Merged = CreateLoadStoreMulti(MBB, InsertBefore, Offset, Base, BaseKill,  in MergeOpsUpdate()
1293   bool BaseKill = BaseOP.isKill();  in MergeBaseUpdateLSMultiple()  local
1325       if (!STI->hasMinSize() || !BaseKill)  in MergeBaseUpdateLSMultiple()
1349     .addReg(Base, getKillRegState(BaseKill))  in MergeBaseUpdateLSMultiple()
1473   bool BaseKill = getLoadStoreBaseOp(*MI).isKill();  in MergeBaseUpdateLoadStore()  local
1530                    .addReg(Base, getKillRegState(isLd ? BaseKill : false))  in MergeBaseUpdateLoadStore()
1734                           bool BaseKill, bool BaseUndef, ARMCC::CondCodes Pred,  in InsertLDR_STR()  argument
1741       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1750       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));  in InsertLDR_STR()
1793   bool BaseKill = BaseOp.isKill();  in FixInvalidRegPairOp()  local
1809         .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1817         .addReg(BaseReg, getKillRegState(BaseKill))  in FixInvalidRegPairOp()
1843                     false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()
1860                     OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,  in FixInvalidRegPairOp()