Lines Matching refs:Shuffle
8098 SDValue Shuffle = buildLegalVectorShuffle(ShuffleVT, dl, ShuffleOps[0], in ReconstructShuffle() local
8100 if (!Shuffle) in ReconstructShuffle()
8102 return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, Shuffle); in ReconstructShuffle()
15652 if (auto *Shuffle = dyn_cast<ShuffleVectorSDNode>(Trunc.getOperand(0))) in PerformSplittingToNarrowingStores() local
15653 if (isVMOVNShuffle(Shuffle, false) || isVMOVNShuffle(Shuffle, true)) in PerformSplittingToNarrowingStores()
18118 Instruction *Shuffle = Op; in shouldSinkOperands() local
18119 if (Shuffle->getOpcode() == Instruction::BitCast) in shouldSinkOperands()
18120 Shuffle = dyn_cast<Instruction>(Shuffle->getOperand(0)); in shouldSinkOperands()
18122 if (!Shuffle || in shouldSinkOperands()
18123 !match(Shuffle, m_Shuffle( in shouldSinkOperands()
18138 Ops.push_back(&Shuffle->getOperandUse(0)); in shouldSinkOperands()
18139 if (Shuffle != Op) in shouldSinkOperands()