9037   SDValue Ext1 = Ext.getValue(1);  in LowerVectorExtend()  local
9041     Ext1 = DAG.getNode(N->getOpcode(), DL, MVT::v8i32, Ext1);  in LowerVectorExtend()
9044   return DAG.getNode(ISD::CONCAT_VECTORS, DL, ToVT, Ext, Ext1);  in LowerVectorExtend()
9966     SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,  in LowerVecReduce()  local
9972     SDValue Res0 = DAG.getNode(BaseOpcode, dl, EltVT, Ext0, Ext1, Op->getFlags());  in LowerVecReduce()
9978     SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,  in LowerVecReduce()  local
9980     Res = DAG.getNode(BaseOpcode, dl, EltVT, Ext0, Ext1, Op->getFlags());  in LowerVecReduce()
12920   SDValue Ext1 = Mul.getOperand(1);  in PerformVQDMULHCombine()  local
12922       Ext1.getOpcode() != ISD::SIGN_EXTEND)  in PerformVQDMULHCombine()
12927   if (Ext1.getOperand(0).getValueType() != VecVT ||  in PerformVQDMULHCombine()
12944         DAG.getNode(ISD::ANY_EXTEND, DL, ExtVecVT, Ext1.getOperand(0));  in PerformVQDMULHCombine()
12962         DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LegalVecVT, Ext1.getOperand(0),  in PerformVQDMULHCombine()
16110       SDValue Ext1 =  in PerformVECREDUCE_ADDCombine()  local
16115                                  Ext0, Ext1);  in PerformVECREDUCE_ADDCombine()
16119                       Ext0.getValue(1), Ext1.getValue(1));  in PerformVECREDUCE_ADDCombine()
18014 static bool areExtractExts(Value *Ext1, Value *Ext2) {  in areExtractExts()  argument
18020   if (!match(Ext1, m_ZExtOrSExt(m_Value())) ||  in areExtractExts()
18022       !areExtDoubled(cast<Instruction>(Ext1)) ||  in areExtractExts()