Lines Matching refs:ArgValue
4226 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); in GetF64FormalArgument() local
4243 std::swap (ArgValue, ArgValue2); in GetF64FormalArgument()
4244 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); in GetF64FormalArgument()
4381 SDValue ArgValue; in LowerFormalArguments() local
4453 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerFormalArguments()
4454 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue, in LowerFormalArguments()
4456 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue, in LowerFormalArguments()
4459 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); in LowerFormalArguments()
4481 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
4497 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
4500 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
4502 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
4505 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
4507 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
4516 ArgValue = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), ArgValue); in LowerFormalArguments()
4518 InVals.push_back(ArgValue); in LowerFormalArguments()