Lines Matching refs:isPre

1592   bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);  in tryARMIndexedLoad()  local
1595 if (LoadedVT == MVT::i32 && isPre && in tryARMIndexedLoad()
1599 } else if (LoadedVT == MVT::i32 && !isPre && in tryARMIndexedLoad()
1605 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG; in tryARMIndexedLoad()
1612 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) in tryARMIndexedLoad()
1613 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); in tryARMIndexedLoad()
1618 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; in tryARMIndexedLoad()
1621 if (isPre && in tryARMIndexedLoad()
1625 } else if (!isPre && in tryARMIndexedLoad()
1631 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG; in tryARMIndexedLoad()
1699 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryT2IndexedLoad() local
1705 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST; in tryT2IndexedLoad()
1709 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST; in tryT2IndexedLoad()
1711 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST; in tryT2IndexedLoad()
1716 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST; in tryT2IndexedLoad()
1718 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST; in tryT2IndexedLoad()
1744 bool isSExtLd, isPre; in tryMVEIndexedLoad() local
1763 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
1779 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
1794 Opcode = isPre ? ARM::MVE_VLDRHS32_pre : ARM::MVE_VLDRHS32_post; in tryMVEIndexedLoad()
1796 Opcode = isPre ? ARM::MVE_VLDRHU32_pre : ARM::MVE_VLDRHU32_post; in tryMVEIndexedLoad()
1800 Opcode = isPre ? ARM::MVE_VLDRBS16_pre : ARM::MVE_VLDRBS16_post; in tryMVEIndexedLoad()
1802 Opcode = isPre ? ARM::MVE_VLDRBU16_pre : ARM::MVE_VLDRBU16_post; in tryMVEIndexedLoad()
1806 Opcode = isPre ? ARM::MVE_VLDRBS32_pre : ARM::MVE_VLDRBS32_post; in tryMVEIndexedLoad()
1808 Opcode = isPre ? ARM::MVE_VLDRBU32_pre : ARM::MVE_VLDRBU32_post; in tryMVEIndexedLoad()
1813 Opcode = isPre ? ARM::MVE_VLDRWU32_pre : ARM::MVE_VLDRWU32_post; in tryMVEIndexedLoad()
1818 Opcode = isPre ? ARM::MVE_VLDRHU16_pre : ARM::MVE_VLDRHU16_post; in tryMVEIndexedLoad()
1821 Opcode = isPre ? ARM::MVE_VLDRBU8_pre : ARM::MVE_VLDRBU8_post; in tryMVEIndexedLoad()