213   void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
221   void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
229                        unsigned NumVecs, const uint16_t *DOpcodes,
286   void SelectMVE_VLD(SDNode *N, unsigned NumVecs,
307                     unsigned NumVecs, const uint16_t *DOpcodes,
345   SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1931                                        unsigned NumVecs, bool is64BitVector) {  in GetVLDSTAlign()  argument
1932   unsigned NumRegs = NumVecs;  in GetVLDSTAlign()
1933   if (!is64BitVector && NumVecs < 3)  in GetVLDSTAlign()
2096 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) {  in isPerfectIncrement()  argument
2098   return C && C->getZExtValue() == VecTy.getSizeInBits() / 8 * NumVecs;  in isPerfectIncrement()
2101 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,  in SelectVLD()  argument
2106   assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");  in SelectVLD()
2119   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);  in SelectVLD()
2144   if (NumVecs == 1)  in SelectVLD()
2147     unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;  in SelectVLD()
2164   if (is64BitVector || NumVecs <= 2) {  in SelectVLD()
2171       bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);  in SelectVLD()
2223   if (NumVecs == 1) {  in SelectVLD()
2234   for (unsigned Vec = 0; Vec < NumVecs; ++Vec)  in SelectVLD()
2237   ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));  in SelectVLD()
2239     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));  in SelectVLD()
2243 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,  in SelectVST()  argument
2248   assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");  in SelectVST()
2264   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);  in SelectVST()
2298   if (is64BitVector || NumVecs <= 2) {  in SelectVST()
2300     if (NumVecs == 1) {  in SelectVST()
2306       if (NumVecs == 2)  in SelectVST()
2312         SDValue V3 = (NumVecs == 3)  in SelectVST()
2330       bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);  in SelectVST()
2363   SDValue V3 = (NumVecs == 3)  in SelectVST()
2398                                       unsigned NumVecs,  in SelectVLDSTLane()  argument
2402   assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");  in SelectVLDSTLane()
2417     cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();  in SelectVLDSTLane()
2422   if (NumVecs != 3) {  in SelectVLDSTLane()
2424     unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;  in SelectVLDSTLane()
2456     unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;  in SelectVLDSTLane()
2475         isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);  in SelectVLDSTLane()
2482   if (NumVecs == 2) {  in SelectVLDSTLane()
2489     SDValue V3 = (NumVecs == 3)  in SelectVLDSTLane()
2518   for (unsigned Vec = 0; Vec < NumVecs; ++Vec)  in SelectVLDSTLane()
2521   ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));  in SelectVLDSTLane()
2523     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));  in SelectVLDSTLane()
2777 void ARMDAGToDAGISel::SelectMVE_VLD(SDNode *N, unsigned NumVecs,  in SelectMVE_VLD()  argument
2798   EVT DataTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, NumVecs * 2);  in SelectMVE_VLD()
2806   for (unsigned Stage = 0; Stage < NumVecs - 1; ++Stage) {  in SelectMVE_VLD()
2819       CurDAG->getMachineNode(OurOpcodes[NumVecs - 1], Loc, ResultTys, Ops);  in SelectMVE_VLD()
2823   for (i = 0; i < NumVecs; i++)  in SelectMVE_VLD()
2940                                    bool isUpdating, unsigned NumVecs,  in SelectVLDDup()  argument
2945   assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");  in SelectVLDDup()
2958   if (NumVecs != 3) {  in SelectVLDDup()
2960     unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;  in SelectVLDDup()
2992   unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;  in SelectVLDDup()
3010                  : (NumVecs == 1) ? QOpcodes0[OpcodeIndex]  in SelectVLDDup()
3015         isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);  in SelectVLDDup()
3025   if (is64BitVector || NumVecs == 1) {  in SelectVLDDup()
3027   } else if (NumVecs == 2) {  in SelectVLDDup()
3053   if (NumVecs == 1) {  in SelectVLDDup()
3059     for (unsigned Vec = 0; Vec != NumVecs; ++Vec) {  in SelectVLDDup()
3064   ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));  in SelectVLDDup()
3066     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));  in SelectVLDDup()