Lines Matching refs:getSubReg

536     D0 = TRI->getSubReg(Reg, ARM::dsub_0);  in GetDSubRegs()
537 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
538 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
539 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
541 D0 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
542 D1 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
543 D2 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
544 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
546 D0 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
547 D1 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
548 D2 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
549 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
551 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
552 D1 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
553 D2 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
554 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
557 D0 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
558 D1 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
559 D2 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
560 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
601 Register SubReg = TRI->getSubReg(DstReg, SubRegIndex); in ExpandVLD()
1395 unsigned SReg0 = TRI->getSubReg(Reg, ARM::ssub_0); in CMSESaveClearFPRegsV8()
1749 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair()
1750 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair()
1774 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0); in ExpandCMP_SWAP_64()
1775 Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1); in ExpandCMP_SWAP_64()
1776 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0); in ExpandCMP_SWAP_64()
1777 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1); in ExpandCMP_SWAP_64()
2571 Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0); in ExpandMI()
2572 Register D1 = TRI->getSubReg(DstReg, ARM::dsub_1); in ExpandMI()
2603 Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); in ExpandMI()
2604 Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); in ExpandMI()
2983 .addReg(TRI->getSubReg(PairReg, ARM::gsub_0), in ExpandMI()
2985 .addReg(TRI->getSubReg(PairReg, ARM::gsub_1), in ExpandMI()