Lines Matching refs:DstIsDead
580 bool DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandVLD() local
604 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
608 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
610 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
612 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
614 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
676 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
791 bool DstIsDead = false; in ExpandLaneOp() local
793 DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandLaneOp()
796 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
798 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
800 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
802 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
844 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
940 bool DstIsDead = MI.getOperand(0).isDead(); in ExpandMOV32BitImm() local
959 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMOV32BitImm()
966 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMOV32BitImm()
1002 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMOV32BitImm()
2418 bool DstIsDead = MI.getOperand(0).isDead(); in ExpandMI() local
2426 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
2440 bool DstIsDead = MI.getOperand(0).isDead(); in ExpandMI() local
2481 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
2498 bool DstIsDead = MI.getOperand(0).isDead(); in ExpandMI() local
2522 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
2560 bool DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandMI() local
2573 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMI()
2574 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandMI()
2577 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()