3834                                   unsigned DefIdx, unsigned DefAlign) const {  in getVLDMDefCycle()  argument
3835   int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;  in getVLDMDefCycle()
3838     return ItinData->getOperandCycle(DefClass, DefIdx);  in getVLDMDefCycle()
3875                                  unsigned DefIdx, unsigned DefAlign) const {  in getLDMDefCycle()  argument
3876   int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;  in getLDMDefCycle()
3879     return ItinData->getOperandCycle(DefClass, DefIdx);  in getLDMDefCycle()
3978                                     unsigned DefIdx, unsigned DefAlign,  in getOperandLatency()  argument
3984   if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())  in getOperandLatency()
3985     return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
3994     DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in getOperandLatency()
4003     DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);  in getOperandLatency()
4024     DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);  in getOperandLatency()
4078     } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,  in getOperandLatency()
4089                                            unsigned &DefIdx, unsigned &Dist) {  in getBundledDefMI()  argument
4106   DefIdx = Idx;  in getBundledDefMI()
4322                                         unsigned DefIdx,  in getOperandLatency()  argument
4329   const MachineOperand &DefMO = DefMI.getOperand(DefIdx);  in getOperandLatency()
4336         getBundledDefMI(&getRegisterInfo(), &DefMI, Reg, DefIdx, DefAdj);  in getOperandLatency()
4352       ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,  in getOperandLatency()
4358     unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,  in getOperandLatencyImpl()  argument
4398   int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, UseMCID,  in getOperandLatencyImpl()
4418                                     SDNode *DefNode, unsigned DefIdx,  in getOperandLatency()  argument
4432     int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);  in getOperandLatency()
4447   int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,  in getOperandLatency()
4479   } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {  in getOperandLatency()
4766                                              unsigned DefIdx,  in hasHighOperandLatency()  argument
4777       SchedModel.computeOperandLatency(&DefMI, DefIdx, &UseMI, UseIdx);  in hasHighOperandLatency()
4786                                         unsigned DefIdx) const {  in hasLowDefLatency()
4794     int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in hasLowDefLatency()
5327     const MachineInstr &MI, unsigned DefIdx,  in getRegSequenceLikeInputs()  argument
5329   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");  in getRegSequenceLikeInputs()
5354     const MachineInstr &MI, unsigned DefIdx,  in getExtractSubregLikeInputs()  argument
5356   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");  in getExtractSubregLikeInputs()
5370     InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;  in getExtractSubregLikeInputs()
5377     const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,  in getInsertSubregLikeInputs()  argument
5379   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");  in getInsertSubregLikeInputs()