Lines Matching refs:AMDGPU
89 namespace AMDGPU { namespace
684 STI->getFeatureBits().test(AMDGPU::FeatureXNACK)); in getNumExtraSGPRs()
826 if (AMDGPU::isGFX90A(*STI)) { in getDefaultAmdhsaKernelDescriptor()
1021 IdSymbolic[Id] && (Id != ID_XNACK_MASK || !AMDGPU::isGFX10_BEncoding(STI)); in isValidHwreg()
1408 return STI.getFeatureBits()[AMDGPU::FeatureXNACK]; in hasXNACK()
1412 return STI.getFeatureBits()[AMDGPU::FeatureSRAMECC]; in hasSRAMECC()
1416 …return STI.getFeatureBits()[AMDGPU::FeatureMIMG_R128] && !STI.getFeatureBits()[AMDGPU::FeatureR128… in hasMIMG_R128()
1420 return STI.getFeatureBits()[AMDGPU::FeatureGFX10A16]; in hasGFX10A16()
1424 return STI.getFeatureBits()[AMDGPU::FeatureG16]; in hasG16()
1428 return !STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]; in hasPackedD16()
1432 return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands]; in isSI()
1436 return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands]; in isCI()
1440 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; in isVI()
1444 return STI.getFeatureBits()[AMDGPU::FeatureGFX9]; in isGFX9()
1452 return STI.getFeatureBits()[AMDGPU::FeatureGFX10]; in isGFX10()
1458 return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding]; in isGCN3Encoding()
1462 return STI.getFeatureBits()[AMDGPU::FeatureGFX10_AEncoding]; in isGFX10_AEncoding()
1466 return STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]; in isGFX10_BEncoding()
1470 return STI.getFeatureBits()[AMDGPU::FeatureGFX10_3Insts]; in hasGFX10_3Insts()
1474 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; in isGFX90A()
1478 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; in hasArchitectedFlatScratch()
1482 const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID); in isSGPR()
1483 const unsigned FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0); in isSGPR()
1485 Reg == AMDGPU::SCC; in isSGPR()
1496 using namespace AMDGPU; \
1566 return OpType >= AMDGPU::OPERAND_SRC_FIRST && in isSISrcOperand()
1567 OpType <= AMDGPU::OPERAND_SRC_LAST; in isSISrcOperand()
1574 case AMDGPU::OPERAND_REG_IMM_FP32: in isSISrcFPOperand()
1575 case AMDGPU::OPERAND_REG_IMM_FP64: in isSISrcFPOperand()
1576 case AMDGPU::OPERAND_REG_IMM_FP16: in isSISrcFPOperand()
1577 case AMDGPU::OPERAND_REG_IMM_V2FP16: in isSISrcFPOperand()
1578 case AMDGPU::OPERAND_REG_IMM_V2INT16: in isSISrcFPOperand()
1579 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in isSISrcFPOperand()
1580 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in isSISrcFPOperand()
1581 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in isSISrcFPOperand()
1582 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in isSISrcFPOperand()
1583 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in isSISrcFPOperand()
1584 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in isSISrcFPOperand()
1585 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in isSISrcFPOperand()
1586 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: in isSISrcFPOperand()
1587 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in isSISrcFPOperand()
1588 case AMDGPU::OPERAND_REG_IMM_V2FP32: in isSISrcFPOperand()
1589 case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: in isSISrcFPOperand()
1590 case AMDGPU::OPERAND_REG_INLINE_AC_FP64: in isSISrcFPOperand()
1600 return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST && in isSISrcInlinableOperand()
1601 OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST; in isSISrcInlinableOperand()
1608 case AMDGPU::VGPR_LO16RegClassID: in getRegBitWidth()
1609 case AMDGPU::VGPR_HI16RegClassID: in getRegBitWidth()
1610 case AMDGPU::SGPR_LO16RegClassID: in getRegBitWidth()
1611 case AMDGPU::AGPR_LO16RegClassID: in getRegBitWidth()
1613 case AMDGPU::SGPR_32RegClassID: in getRegBitWidth()
1614 case AMDGPU::VGPR_32RegClassID: in getRegBitWidth()
1615 case AMDGPU::VRegOrLds_32RegClassID: in getRegBitWidth()
1616 case AMDGPU::AGPR_32RegClassID: in getRegBitWidth()
1617 case AMDGPU::VS_32RegClassID: in getRegBitWidth()
1618 case AMDGPU::AV_32RegClassID: in getRegBitWidth()
1619 case AMDGPU::SReg_32RegClassID: in getRegBitWidth()
1620 case AMDGPU::SReg_32_XM0RegClassID: in getRegBitWidth()
1621 case AMDGPU::SRegOrLds_32RegClassID: in getRegBitWidth()
1623 case AMDGPU::SGPR_64RegClassID: in getRegBitWidth()
1624 case AMDGPU::VS_64RegClassID: in getRegBitWidth()
1625 case AMDGPU::AV_64RegClassID: in getRegBitWidth()
1626 case AMDGPU::SReg_64RegClassID: in getRegBitWidth()
1627 case AMDGPU::VReg_64RegClassID: in getRegBitWidth()
1628 case AMDGPU::AReg_64RegClassID: in getRegBitWidth()
1629 case AMDGPU::SReg_64_XEXECRegClassID: in getRegBitWidth()
1630 case AMDGPU::VReg_64_Align2RegClassID: in getRegBitWidth()
1631 case AMDGPU::AReg_64_Align2RegClassID: in getRegBitWidth()
1633 case AMDGPU::SGPR_96RegClassID: in getRegBitWidth()
1634 case AMDGPU::SReg_96RegClassID: in getRegBitWidth()
1635 case AMDGPU::VReg_96RegClassID: in getRegBitWidth()
1636 case AMDGPU::AReg_96RegClassID: in getRegBitWidth()
1637 case AMDGPU::VReg_96_Align2RegClassID: in getRegBitWidth()
1638 case AMDGPU::AReg_96_Align2RegClassID: in getRegBitWidth()
1639 case AMDGPU::AV_96RegClassID: in getRegBitWidth()
1641 case AMDGPU::SGPR_128RegClassID: in getRegBitWidth()
1642 case AMDGPU::SReg_128RegClassID: in getRegBitWidth()
1643 case AMDGPU::VReg_128RegClassID: in getRegBitWidth()
1644 case AMDGPU::AReg_128RegClassID: in getRegBitWidth()
1645 case AMDGPU::VReg_128_Align2RegClassID: in getRegBitWidth()
1646 case AMDGPU::AReg_128_Align2RegClassID: in getRegBitWidth()
1647 case AMDGPU::AV_128RegClassID: in getRegBitWidth()
1649 case AMDGPU::SGPR_160RegClassID: in getRegBitWidth()
1650 case AMDGPU::SReg_160RegClassID: in getRegBitWidth()
1651 case AMDGPU::VReg_160RegClassID: in getRegBitWidth()
1652 case AMDGPU::AReg_160RegClassID: in getRegBitWidth()
1653 case AMDGPU::VReg_160_Align2RegClassID: in getRegBitWidth()
1654 case AMDGPU::AReg_160_Align2RegClassID: in getRegBitWidth()
1655 case AMDGPU::AV_160RegClassID: in getRegBitWidth()
1657 case AMDGPU::SGPR_192RegClassID: in getRegBitWidth()
1658 case AMDGPU::SReg_192RegClassID: in getRegBitWidth()
1659 case AMDGPU::VReg_192RegClassID: in getRegBitWidth()
1660 case AMDGPU::AReg_192RegClassID: in getRegBitWidth()
1661 case AMDGPU::VReg_192_Align2RegClassID: in getRegBitWidth()
1662 case AMDGPU::AReg_192_Align2RegClassID: in getRegBitWidth()
1664 case AMDGPU::SGPR_224RegClassID: in getRegBitWidth()
1665 case AMDGPU::SReg_224RegClassID: in getRegBitWidth()
1666 case AMDGPU::VReg_224RegClassID: in getRegBitWidth()
1667 case AMDGPU::AReg_224RegClassID: in getRegBitWidth()
1668 case AMDGPU::VReg_224_Align2RegClassID: in getRegBitWidth()
1669 case AMDGPU::AReg_224_Align2RegClassID: in getRegBitWidth()
1671 case AMDGPU::SGPR_256RegClassID: in getRegBitWidth()
1672 case AMDGPU::SReg_256RegClassID: in getRegBitWidth()
1673 case AMDGPU::VReg_256RegClassID: in getRegBitWidth()
1674 case AMDGPU::AReg_256RegClassID: in getRegBitWidth()
1675 case AMDGPU::VReg_256_Align2RegClassID: in getRegBitWidth()
1676 case AMDGPU::AReg_256_Align2RegClassID: in getRegBitWidth()
1678 case AMDGPU::SGPR_512RegClassID: in getRegBitWidth()
1679 case AMDGPU::SReg_512RegClassID: in getRegBitWidth()
1680 case AMDGPU::VReg_512RegClassID: in getRegBitWidth()
1681 case AMDGPU::AReg_512RegClassID: in getRegBitWidth()
1682 case AMDGPU::VReg_512_Align2RegClassID: in getRegBitWidth()
1683 case AMDGPU::AReg_512_Align2RegClassID: in getRegBitWidth()
1685 case AMDGPU::SGPR_1024RegClassID: in getRegBitWidth()
1686 case AMDGPU::SReg_1024RegClassID: in getRegBitWidth()
1687 case AMDGPU::VReg_1024RegClassID: in getRegBitWidth()
1688 case AMDGPU::AReg_1024RegClassID: in getRegBitWidth()
1689 case AMDGPU::VReg_1024_Align2RegClassID: in getRegBitWidth()
1690 case AMDGPU::AReg_1024_Align2RegClassID: in getRegBitWidth()
1775 return AMDGPU::isInlinableLiteral16(Trunc, HasInv2Pi); in isInlinableLiteralV216()
1778 return AMDGPU::isInlinableLiteral16(Literal >> 16, HasInv2Pi); in isInlinableLiteralV216()
1899 if (AMDGPU::isGFX10(ST)) in getNumFlatOffsetBits()
2021 const AMDGPU::IsaInfo::TargetIDSetting S) { in operator <<()
2023 case (AMDGPU::IsaInfo::TargetIDSetting::Unsupported): in operator <<()
2026 case (AMDGPU::IsaInfo::TargetIDSetting::Any): in operator <<()
2029 case (AMDGPU::IsaInfo::TargetIDSetting::Off): in operator <<()
2032 case (AMDGPU::IsaInfo::TargetIDSetting::On): in operator <<()