66   int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);  in foldImmediates()
186   int SOPKOpc = AMDGPU::getSOPKOp(MI.getOpcode());  in shrinkScalarCompare()
192   if (SOPKOpc == AMDGPU::S_CMPK_EQ_U32 || SOPKOpc == AMDGPU::S_CMPK_LG_U32) {  in shrinkScalarCompare()
196         SOPKOpc = (SOPKOpc == AMDGPU::S_CMPK_EQ_U32) ?  in shrinkScalarCompare()
197           AMDGPU::S_CMPK_EQ_I32 : AMDGPU::S_CMPK_LG_I32;  in shrinkScalarCompare()
216   const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());  in shrinkMIMG()
217   if (!Info || Info->MIMGEncoding != AMDGPU::MIMGEncGfx10NSA)  in shrinkMIMG()
225       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);  in shrinkMIMG()
230     RC = &AMDGPU::VReg_64RegClass;  in shrinkMIMG()
232     RC = &AMDGPU::VReg_96RegClass;  in shrinkMIMG()
234     RC = &AMDGPU::VReg_128RegClass;  in shrinkMIMG()
236     RC = &AMDGPU::VReg_160RegClass;  in shrinkMIMG()
238     RC = &AMDGPU::VReg_192RegClass;  in shrinkMIMG()
240     RC = &AMDGPU::VReg_224RegClass;  in shrinkMIMG()
242     RC = &AMDGPU::VReg_256RegClass;  in shrinkMIMG()
244     RC = &AMDGPU::VReg_512RegClass;  in shrinkMIMG()
271   int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe);  in shrinkMIMG()
272   int LWEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::lwe);  in shrinkMIMG()
292       AMDGPU::getMIMGOpcode(Info->BaseOpcode, AMDGPU::MIMGEncGfx10Default,  in shrinkMIMG()
304         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdata),  in shrinkMIMG()
326       AMDGPU::isInlinableLiteral32(SrcImm->getImm(), ST.hasInv2PiInlineImm()))  in shrinkScalarLogicOp()
332   if (Opc == AMDGPU::S_AND_B32) {  in shrinkScalarLogicOp()
335       Opc = AMDGPU::S_BITSET0_B32;  in shrinkScalarLogicOp()
336     } else if (AMDGPU::isInlinableLiteral32(~Imm, ST.hasInv2PiInlineImm())) {  in shrinkScalarLogicOp()
338       Opc = AMDGPU::S_ANDN2_B32;  in shrinkScalarLogicOp()
340   } else if (Opc == AMDGPU::S_OR_B32) {  in shrinkScalarLogicOp()
343       Opc = AMDGPU::S_BITSET1_B32;  in shrinkScalarLogicOp()
344     } else if (AMDGPU::isInlinableLiteral32(~Imm, ST.hasInv2PiInlineImm())) {  in shrinkScalarLogicOp()
346       Opc = AMDGPU::S_ORN2_B32;  in shrinkScalarLogicOp()
348   } else if (Opc == AMDGPU::S_XOR_B32) {  in shrinkScalarLogicOp()
349     if (AMDGPU::isInlinableLiteral32(~Imm, ST.hasInv2PiInlineImm())) {  in shrinkScalarLogicOp()
351       Opc = AMDGPU::S_XNOR_B32;  in shrinkScalarLogicOp()
357   if ((Opc == AMDGPU::S_ANDN2_B32 || Opc == AMDGPU::S_ORN2_B32) &&  in shrinkScalarLogicOp()
374       if (Opc == AMDGPU::S_BITSET0_B32 ||  in shrinkScalarLogicOp()
375           Opc == AMDGPU::S_BITSET1_B32) {  in shrinkScalarLogicOp()
448             TII->get(AMDGPU::IMPLICIT_DEF), Op.getReg());  in dropInstructionKeepingImpDefs()
475   assert(MovT.getOpcode() == AMDGPU::V_MOV_B32_e32 ||  in matchSwap()
476          MovT.getOpcode() == AMDGPU::COPY);  in matchSwap()
493   if (MovT.hasRegisterImplicitUseOperand(AMDGPU::M0))  in matchSwap()
506     if ((MovY->getOpcode() != AMDGPU::V_MOV_B32_e32 &&  in matchSwap()
507          MovY->getOpcode() != AMDGPU::COPY) ||  in matchSwap()
511         MovY->hasRegisterImplicitUseOperand(AMDGPU::M0))  in matchSwap()
538           (I->getOpcode() != AMDGPU::V_MOV_B32_e32 &&  in matchSwap()
539            I->getOpcode() != AMDGPU::COPY) ||  in matchSwap()
546       if (I->hasRegisterImplicitUseOperand(AMDGPU::M0))  in matchSwap()
566                          TII->get(AMDGPU::V_SWAP_B32))  in matchSwap()
571       if (MovX->hasRegisterImplicitUseOperand(AMDGPU::EXEC)) {  in matchSwap()
606   unsigned VCCReg = ST.isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC;  in runOnMachineFunction()
619       if (MI.getOpcode() == AMDGPU::V_MOV_B32_e32) {  in runOnMachineFunction()
632             MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32));  in runOnMachineFunction()
639       if (ST.hasSwap() && (MI.getOpcode() == AMDGPU::V_MOV_B32_e32 ||  in runOnMachineFunction()
640                            MI.getOpcode() == AMDGPU::COPY)) {  in runOnMachineFunction()
652       if (MI.getOpcode() == AMDGPU::S_ADD_I32 ||  in runOnMachineFunction()
653           MI.getOpcode() == AMDGPU::S_MUL_I32) {  in runOnMachineFunction()
674             unsigned Opc = (MI.getOpcode() == AMDGPU::S_ADD_I32) ?  in runOnMachineFunction()
675               AMDGPU::S_ADDK_I32 : AMDGPU::S_MULK_I32;  in runOnMachineFunction()
690       if (MI.getOpcode() == AMDGPU::S_MOV_B32) {  in runOnMachineFunction()
697             MI.setDesc(TII->get(AMDGPU::S_MOVK_I32));  in runOnMachineFunction()
699             MI.setDesc(TII->get(AMDGPU::S_BREV_B32));  in runOnMachineFunction()
708       if (MI.getOpcode() == AMDGPU::S_AND_B32 ||  in runOnMachineFunction()
709           MI.getOpcode() == AMDGPU::S_OR_B32 ||  in runOnMachineFunction()
710           MI.getOpcode() == AMDGPU::S_XOR_B32) {  in runOnMachineFunction()
739       int Op32 = AMDGPU::getVOPe32(MI.getOpcode());  in runOnMachineFunction()
759       if (Op32 == AMDGPU::V_CNDMASK_B32_e32) {  in runOnMachineFunction()
763             TII->getNamedOperand(MI, AMDGPU::OpName::src2);  in runOnMachineFunction()
777                                                         AMDGPU::OpName::sdst);  in runOnMachineFunction()
781                                                         AMDGPU::OpName::src2);  in runOnMachineFunction()