Lines Matching refs:AMDGPU
88 Register TmpVGPR = AMDGPU::NoRegister;
94 Register SavedExecReg = AMDGPU::NoRegister;
123 ExecReg = AMDGPU::EXEC_LO; in SGPRSpillBuilder()
124 MovOpc = AMDGPU::S_MOV_B32; in SGPRSpillBuilder()
125 NotOpc = AMDGPU::S_NOT_B32; in SGPRSpillBuilder()
127 ExecReg = AMDGPU::EXEC; in SGPRSpillBuilder()
128 MovOpc = AMDGPU::S_MOV_B64; in SGPRSpillBuilder()
129 NotOpc = AMDGPU::S_NOT_B64; in SGPRSpillBuilder()
132 assert(SuperReg != AMDGPU::M0 && "m0 should never spill"); in SGPRSpillBuilder()
133 assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI && in SGPRSpillBuilder()
134 SuperReg != AMDGPU::EXEC && "exec should never spill"); in SGPRSpillBuilder()
166 TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0, false); in prepare()
176 TmpVGPR = AMDGPU::VGPR0; in prepare()
183 IsWave32 ? AMDGPU::SGPR_32RegClass : AMDGPU::SGPR_64RegClass; in prepare()
274 : AMDGPUGenRegisterInfo(AMDGPU::PC_REG, ST.getAMDGPUDwarfFlavour()), ST(ST), in SIRegisterInfo()
277 assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 && in SIRegisterInfo()
278 getSubRegIndexLaneMask(AMDGPU::sub31).getAsInteger() == (3ULL << 62) && in SIRegisterInfo()
279 (getSubRegIndexLaneMask(AMDGPU::lo16) | in SIRegisterInfo()
280 getSubRegIndexLaneMask(AMDGPU::hi16)).getAsInteger() == in SIRegisterInfo()
281 getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() && in SIRegisterInfo()
286 *MCRegUnitIterator(MCRegister::from(AMDGPU::M0), this)); in SIRegisterInfo()
287 for (auto Reg : AMDGPU::VGPR_HI16RegClass) in SIRegisterInfo()
315 Row.fill(AMDGPU::NoSubRegister); in SIRegisterInfo()
357 static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister; in getCalleeSavedRegs()
409 Register SIRegisterInfo::getBaseRegister() const { return AMDGPU::SGPR34; } in getBaseRegister()
439 MCRegister BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx)); in reservedPrivateSegmentBufferReg()
440 return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SGPR_128RegClass); in reservedPrivateSegmentBufferReg()
445 Reserved.set(AMDGPU::MODE); in getReservedRegs()
449 reserveRegisterTuples(Reserved, AMDGPU::EXEC); in getReservedRegs()
450 reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR); in getReservedRegs()
453 reserveRegisterTuples(Reserved, AMDGPU::M0); in getReservedRegs()
456 reserveRegisterTuples(Reserved, AMDGPU::SRC_VCCZ); in getReservedRegs()
457 reserveRegisterTuples(Reserved, AMDGPU::SRC_EXECZ); in getReservedRegs()
458 reserveRegisterTuples(Reserved, AMDGPU::SRC_SCC); in getReservedRegs()
461 reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_BASE); in getReservedRegs()
462 reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_LIMIT); in getReservedRegs()
463 reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_BASE); in getReservedRegs()
464 reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_LIMIT); in getReservedRegs()
467 reserveRegisterTuples(Reserved, AMDGPU::SRC_POPS_EXITING_WAVE_ID); in getReservedRegs()
470 reserveRegisterTuples(Reserved, AMDGPU::XNACK_MASK); in getReservedRegs()
473 reserveRegisterTuples(Reserved, AMDGPU::LDS_DIRECT); in getReservedRegs()
476 reserveRegisterTuples(Reserved, AMDGPU::TBA); in getReservedRegs()
477 reserveRegisterTuples(Reserved, AMDGPU::TMA); in getReservedRegs()
478 reserveRegisterTuples(Reserved, AMDGPU::TTMP0_TTMP1); in getReservedRegs()
479 reserveRegisterTuples(Reserved, AMDGPU::TTMP2_TTMP3); in getReservedRegs()
480 reserveRegisterTuples(Reserved, AMDGPU::TTMP4_TTMP5); in getReservedRegs()
481 reserveRegisterTuples(Reserved, AMDGPU::TTMP6_TTMP7); in getReservedRegs()
482 reserveRegisterTuples(Reserved, AMDGPU::TTMP8_TTMP9); in getReservedRegs()
483 reserveRegisterTuples(Reserved, AMDGPU::TTMP10_TTMP11); in getReservedRegs()
484 reserveRegisterTuples(Reserved, AMDGPU::TTMP12_TTMP13); in getReservedRegs()
485 reserveRegisterTuples(Reserved, AMDGPU::TTMP14_TTMP15); in getReservedRegs()
488 reserveRegisterTuples(Reserved, AMDGPU::SGPR_NULL); in getReservedRegs()
493 Reserved.set(AMDGPU::VCC); in getReservedRegs()
494 Reserved.set(AMDGPU::VCC_HI); in getReservedRegs()
498 unsigned TotalNumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs(); in getReservedRegs()
500 unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i); in getReservedRegs()
511 unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs(); in getReservedRegs()
513 unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i); in getReservedRegs()
515 Reg = AMDGPU::AGPR_32RegClass.getRegister(i); in getReservedRegs()
519 for (auto Reg : AMDGPU::SReg_32RegClass) { in getReservedRegs()
520 Reserved.set(getSubReg(Reg, AMDGPU::hi16)); in getReservedRegs()
521 Register Low = getSubReg(Reg, AMDGPU::lo16); in getReservedRegs()
523 if (!AMDGPU::SGPR_LO16RegClass.contains(Low)) in getReservedRegs()
527 for (auto Reg : AMDGPU::AGPR_32RegClass) { in getReservedRegs()
528 Reserved.set(getSubReg(Reg, AMDGPU::hi16)); in getReservedRegs()
534 unsigned Reg = AMDGPU::AGPR_32RegClass.getRegister(i); in getReservedRegs()
542 if (ScratchRSrcReg != AMDGPU::NoRegister) { in getReservedRegs()
647 int OffIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), in getScratchInstrOffset()
648 AMDGPU::OpName::offset); in getScratchInstrOffset()
657 assert((Idx == AMDGPU::getNamedOperandIdx(MI->getOpcode(), in getFrameIndexInstrOffset()
658 AMDGPU::OpName::vaddr) || in getFrameIndexInstrOffset()
659 (Idx == AMDGPU::getNamedOperandIdx(MI->getOpcode(), in getFrameIndexInstrOffset()
660 AMDGPU::OpName::saddr))) && in getFrameIndexInstrOffset()
692 unsigned MovOpc = ST.enableFlatScratch() ? AMDGPU::S_MOV_B32 in materializeFrameBaseRegister()
693 : AMDGPU::V_MOV_B32_e32; in materializeFrameBaseRegister()
696 ST.enableFlatScratch() ? &AMDGPU::SReg_32_XEXEC_HIRegClass in materializeFrameBaseRegister()
697 : &AMDGPU::VGPR_32RegClass); in materializeFrameBaseRegister()
705 Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in materializeFrameBaseRegister()
708 ST.enableFlatScratch() ? &AMDGPU::SReg_32_XM0RegClass in materializeFrameBaseRegister()
709 : &AMDGPU::VGPR_32RegClass); in materializeFrameBaseRegister()
711 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in materializeFrameBaseRegister()
717 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_ADD_I32), BaseReg) in materializeFrameBaseRegister()
750 TII->getNamedOperand(MI, IsFlat ? AMDGPU::OpName::saddr in resolveFrameIndex()
751 : AMDGPU::OpName::vaddr); in resolveFrameIndex()
753 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset); in resolveFrameIndex()
769 MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in resolveFrameIndex()
801 return &AMDGPU::VGPR_32RegClass; in getPointerRegClass()
807 case AMDGPU::SI_SPILL_S1024_SAVE: in getNumSubRegsForSpillOp()
808 case AMDGPU::SI_SPILL_S1024_RESTORE: in getNumSubRegsForSpillOp()
809 case AMDGPU::SI_SPILL_V1024_SAVE: in getNumSubRegsForSpillOp()
810 case AMDGPU::SI_SPILL_V1024_RESTORE: in getNumSubRegsForSpillOp()
811 case AMDGPU::SI_SPILL_A1024_SAVE: in getNumSubRegsForSpillOp()
812 case AMDGPU::SI_SPILL_A1024_RESTORE: in getNumSubRegsForSpillOp()
814 case AMDGPU::SI_SPILL_S512_SAVE: in getNumSubRegsForSpillOp()
815 case AMDGPU::SI_SPILL_S512_RESTORE: in getNumSubRegsForSpillOp()
816 case AMDGPU::SI_SPILL_V512_SAVE: in getNumSubRegsForSpillOp()
817 case AMDGPU::SI_SPILL_V512_RESTORE: in getNumSubRegsForSpillOp()
818 case AMDGPU::SI_SPILL_A512_SAVE: in getNumSubRegsForSpillOp()
819 case AMDGPU::SI_SPILL_A512_RESTORE: in getNumSubRegsForSpillOp()
821 case AMDGPU::SI_SPILL_S256_SAVE: in getNumSubRegsForSpillOp()
822 case AMDGPU::SI_SPILL_S256_RESTORE: in getNumSubRegsForSpillOp()
823 case AMDGPU::SI_SPILL_V256_SAVE: in getNumSubRegsForSpillOp()
824 case AMDGPU::SI_SPILL_V256_RESTORE: in getNumSubRegsForSpillOp()
825 case AMDGPU::SI_SPILL_A256_SAVE: in getNumSubRegsForSpillOp()
826 case AMDGPU::SI_SPILL_A256_RESTORE: in getNumSubRegsForSpillOp()
828 case AMDGPU::SI_SPILL_S224_SAVE: in getNumSubRegsForSpillOp()
829 case AMDGPU::SI_SPILL_S224_RESTORE: in getNumSubRegsForSpillOp()
830 case AMDGPU::SI_SPILL_V224_SAVE: in getNumSubRegsForSpillOp()
831 case AMDGPU::SI_SPILL_V224_RESTORE: in getNumSubRegsForSpillOp()
832 case AMDGPU::SI_SPILL_A224_SAVE: in getNumSubRegsForSpillOp()
833 case AMDGPU::SI_SPILL_A224_RESTORE: in getNumSubRegsForSpillOp()
835 case AMDGPU::SI_SPILL_S192_SAVE: in getNumSubRegsForSpillOp()
836 case AMDGPU::SI_SPILL_S192_RESTORE: in getNumSubRegsForSpillOp()
837 case AMDGPU::SI_SPILL_V192_SAVE: in getNumSubRegsForSpillOp()
838 case AMDGPU::SI_SPILL_V192_RESTORE: in getNumSubRegsForSpillOp()
839 case AMDGPU::SI_SPILL_A192_SAVE: in getNumSubRegsForSpillOp()
840 case AMDGPU::SI_SPILL_A192_RESTORE: in getNumSubRegsForSpillOp()
842 case AMDGPU::SI_SPILL_S160_SAVE: in getNumSubRegsForSpillOp()
843 case AMDGPU::SI_SPILL_S160_RESTORE: in getNumSubRegsForSpillOp()
844 case AMDGPU::SI_SPILL_V160_SAVE: in getNumSubRegsForSpillOp()
845 case AMDGPU::SI_SPILL_V160_RESTORE: in getNumSubRegsForSpillOp()
846 case AMDGPU::SI_SPILL_A160_SAVE: in getNumSubRegsForSpillOp()
847 case AMDGPU::SI_SPILL_A160_RESTORE: in getNumSubRegsForSpillOp()
849 case AMDGPU::SI_SPILL_S128_SAVE: in getNumSubRegsForSpillOp()
850 case AMDGPU::SI_SPILL_S128_RESTORE: in getNumSubRegsForSpillOp()
851 case AMDGPU::SI_SPILL_V128_SAVE: in getNumSubRegsForSpillOp()
852 case AMDGPU::SI_SPILL_V128_RESTORE: in getNumSubRegsForSpillOp()
853 case AMDGPU::SI_SPILL_A128_SAVE: in getNumSubRegsForSpillOp()
854 case AMDGPU::SI_SPILL_A128_RESTORE: in getNumSubRegsForSpillOp()
856 case AMDGPU::SI_SPILL_S96_SAVE: in getNumSubRegsForSpillOp()
857 case AMDGPU::SI_SPILL_S96_RESTORE: in getNumSubRegsForSpillOp()
858 case AMDGPU::SI_SPILL_V96_SAVE: in getNumSubRegsForSpillOp()
859 case AMDGPU::SI_SPILL_V96_RESTORE: in getNumSubRegsForSpillOp()
860 case AMDGPU::SI_SPILL_A96_SAVE: in getNumSubRegsForSpillOp()
861 case AMDGPU::SI_SPILL_A96_RESTORE: in getNumSubRegsForSpillOp()
863 case AMDGPU::SI_SPILL_S64_SAVE: in getNumSubRegsForSpillOp()
864 case AMDGPU::SI_SPILL_S64_RESTORE: in getNumSubRegsForSpillOp()
865 case AMDGPU::SI_SPILL_V64_SAVE: in getNumSubRegsForSpillOp()
866 case AMDGPU::SI_SPILL_V64_RESTORE: in getNumSubRegsForSpillOp()
867 case AMDGPU::SI_SPILL_A64_SAVE: in getNumSubRegsForSpillOp()
868 case AMDGPU::SI_SPILL_A64_RESTORE: in getNumSubRegsForSpillOp()
870 case AMDGPU::SI_SPILL_S32_SAVE: in getNumSubRegsForSpillOp()
871 case AMDGPU::SI_SPILL_S32_RESTORE: in getNumSubRegsForSpillOp()
872 case AMDGPU::SI_SPILL_V32_SAVE: in getNumSubRegsForSpillOp()
873 case AMDGPU::SI_SPILL_V32_RESTORE: in getNumSubRegsForSpillOp()
874 case AMDGPU::SI_SPILL_A32_SAVE: in getNumSubRegsForSpillOp()
875 case AMDGPU::SI_SPILL_A32_RESTORE: in getNumSubRegsForSpillOp()
883 case AMDGPU::BUFFER_STORE_DWORD_OFFEN: in getOffsetMUBUFStore()
884 return AMDGPU::BUFFER_STORE_DWORD_OFFSET; in getOffsetMUBUFStore()
885 case AMDGPU::BUFFER_STORE_BYTE_OFFEN: in getOffsetMUBUFStore()
886 return AMDGPU::BUFFER_STORE_BYTE_OFFSET; in getOffsetMUBUFStore()
887 case AMDGPU::BUFFER_STORE_SHORT_OFFEN: in getOffsetMUBUFStore()
888 return AMDGPU::BUFFER_STORE_SHORT_OFFSET; in getOffsetMUBUFStore()
889 case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN: in getOffsetMUBUFStore()
890 return AMDGPU::BUFFER_STORE_DWORDX2_OFFSET; in getOffsetMUBUFStore()
891 case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN: in getOffsetMUBUFStore()
892 return AMDGPU::BUFFER_STORE_DWORDX4_OFFSET; in getOffsetMUBUFStore()
893 case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN: in getOffsetMUBUFStore()
894 return AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET; in getOffsetMUBUFStore()
895 case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN: in getOffsetMUBUFStore()
896 return AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET; in getOffsetMUBUFStore()
904 case AMDGPU::BUFFER_LOAD_DWORD_OFFEN: in getOffsetMUBUFLoad()
905 return AMDGPU::BUFFER_LOAD_DWORD_OFFSET; in getOffsetMUBUFLoad()
906 case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN: in getOffsetMUBUFLoad()
907 return AMDGPU::BUFFER_LOAD_UBYTE_OFFSET; in getOffsetMUBUFLoad()
908 case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN: in getOffsetMUBUFLoad()
909 return AMDGPU::BUFFER_LOAD_SBYTE_OFFSET; in getOffsetMUBUFLoad()
910 case AMDGPU::BUFFER_LOAD_USHORT_OFFEN: in getOffsetMUBUFLoad()
911 return AMDGPU::BUFFER_LOAD_USHORT_OFFSET; in getOffsetMUBUFLoad()
912 case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN: in getOffsetMUBUFLoad()
913 return AMDGPU::BUFFER_LOAD_SSHORT_OFFSET; in getOffsetMUBUFLoad()
914 case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN: in getOffsetMUBUFLoad()
915 return AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET; in getOffsetMUBUFLoad()
916 case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN: in getOffsetMUBUFLoad()
917 return AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET; in getOffsetMUBUFLoad()
918 case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN: in getOffsetMUBUFLoad()
919 return AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET; in getOffsetMUBUFLoad()
920 case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN: in getOffsetMUBUFLoad()
921 return AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET; in getOffsetMUBUFLoad()
922 case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN: in getOffsetMUBUFLoad()
923 return AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET; in getOffsetMUBUFLoad()
924 case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN: in getOffsetMUBUFLoad()
925 return AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET; in getOffsetMUBUFLoad()
926 case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN: in getOffsetMUBUFLoad()
927 return AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET; in getOffsetMUBUFLoad()
928 case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN: in getOffsetMUBUFLoad()
929 return AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET; in getOffsetMUBUFLoad()
946 if (Reg == AMDGPU::NoRegister) in spillVGPRtoAGPR()
955 unsigned Opc = (IsStore ^ TRI->isVGPR(MRI, Reg)) ? AMDGPU::V_ACCVGPR_WRITE_B32_e64 in spillVGPRtoAGPR()
956 : AMDGPU::V_ACCVGPR_READ_B32_e64; in spillVGPRtoAGPR()
982 const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata); in buildMUBUFOffsetLoadStore()
989 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)) in buildMUBUFOffsetLoadStore()
990 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)) in buildMUBUFOffsetLoadStore()
998 AMDGPU::OpName::vdata_in); in buildMUBUFOffsetLoadStore()
1009 AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::vaddr) < 0 && in getFlatScratchSpillOpcode()
1010 AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::saddr) < 0; in getFlatScratchSpillOpcode()
1014 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORD_SADDR in getFlatScratchSpillOpcode()
1015 : AMDGPU::SCRATCH_LOAD_DWORD_SADDR; in getFlatScratchSpillOpcode()
1018 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX2_SADDR in getFlatScratchSpillOpcode()
1019 : AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR; in getFlatScratchSpillOpcode()
1022 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX3_SADDR in getFlatScratchSpillOpcode()
1023 : AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR; in getFlatScratchSpillOpcode()
1026 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX4_SADDR in getFlatScratchSpillOpcode()
1027 : AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR; in getFlatScratchSpillOpcode()
1034 LoadStoreOp = AMDGPU::getFlatScratchInstSTfromSS(LoadStoreOp); in getFlatScratchSpillOpcode()
1062 const unsigned RegWidth = AMDGPU::getRegBitWidth(RC->getID()) / 8; in buildSpillLoadStore()
1102 SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0, false); in buildSpillLoadStore()
1104 for (MCRegister Reg : AMDGPU::SGPR_32RegClass) { in buildSpillLoadStore()
1131 if (ScratchOffsetReg == AMDGPU::NoRegister) { in buildSpillLoadStore()
1132 BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), SOffset).addImm(Offset); in buildSpillLoadStore()
1134 BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), SOffset) in buildSpillLoadStore()
1142 if (IsFlat && SOffset == AMDGPU::NoRegister) { in buildSpillLoadStore()
1143 assert(AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::vaddr) < 0 in buildSpillLoadStore()
1147 LoadStoreOp = AMDGPU::getFlatScratchInstSTfromSS(LoadStoreOp); in buildSpillLoadStore()
1229 TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in buildSpillLoadStore()
1234 TII->get(AMDGPU::V_ACCVGPR_READ_B32_e64), TmpReg) in buildSpillLoadStore()
1254 if (SOffset == AMDGPU::NoRegister) { in buildSpillLoadStore()
1270 if (!IsStore && TmpReg != AMDGPU::NoRegister) { in buildSpillLoadStore()
1271 MIB = BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64), in buildSpillLoadStore()
1283 BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), SOffset) in buildSpillLoadStore()
1308 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR in buildVGPRSpillLoadStore()
1309 : AMDGPU::BUFFER_LOAD_DWORD_OFFSET; in buildVGPRSpillLoadStore()
1313 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR in buildVGPRSpillLoadStore()
1314 : AMDGPU::BUFFER_STORE_DWORD_OFFSET; in buildVGPRSpillLoadStore()
1350 auto MIB = BuildMI(SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_WRITELANE_B32), in spillSGPR()
1397 BuildMI(SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_WRITELANE_B32), in spillSGPR()
1460 BuildMI(SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_READLANE_B32), SubReg) in restoreSGPR()
1494 SB.TII.get(AMDGPU::V_READLANE_B32), SubReg) in restoreSGPR()
1528 case AMDGPU::SI_SPILL_S1024_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1529 case AMDGPU::SI_SPILL_S512_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1530 case AMDGPU::SI_SPILL_S256_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1531 case AMDGPU::SI_SPILL_S224_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1532 case AMDGPU::SI_SPILL_S192_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1533 case AMDGPU::SI_SPILL_S160_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1534 case AMDGPU::SI_SPILL_S128_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1535 case AMDGPU::SI_SPILL_S96_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1536 case AMDGPU::SI_SPILL_S64_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1537 case AMDGPU::SI_SPILL_S32_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1539 case AMDGPU::SI_SPILL_S1024_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1540 case AMDGPU::SI_SPILL_S512_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1541 case AMDGPU::SI_SPILL_S256_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1542 case AMDGPU::SI_SPILL_S224_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1543 case AMDGPU::SI_SPILL_S192_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1544 case AMDGPU::SI_SPILL_S160_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1545 case AMDGPU::SI_SPILL_S128_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1546 case AMDGPU::SI_SPILL_S96_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1547 case AMDGPU::SI_SPILL_S64_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1548 case AMDGPU::SI_SPILL_S32_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1576 case AMDGPU::SI_SPILL_S1024_SAVE: in eliminateFrameIndex()
1577 case AMDGPU::SI_SPILL_S512_SAVE: in eliminateFrameIndex()
1578 case AMDGPU::SI_SPILL_S256_SAVE: in eliminateFrameIndex()
1579 case AMDGPU::SI_SPILL_S224_SAVE: in eliminateFrameIndex()
1580 case AMDGPU::SI_SPILL_S192_SAVE: in eliminateFrameIndex()
1581 case AMDGPU::SI_SPILL_S160_SAVE: in eliminateFrameIndex()
1582 case AMDGPU::SI_SPILL_S128_SAVE: in eliminateFrameIndex()
1583 case AMDGPU::SI_SPILL_S96_SAVE: in eliminateFrameIndex()
1584 case AMDGPU::SI_SPILL_S64_SAVE: in eliminateFrameIndex()
1585 case AMDGPU::SI_SPILL_S32_SAVE: { in eliminateFrameIndex()
1591 case AMDGPU::SI_SPILL_S1024_RESTORE: in eliminateFrameIndex()
1592 case AMDGPU::SI_SPILL_S512_RESTORE: in eliminateFrameIndex()
1593 case AMDGPU::SI_SPILL_S256_RESTORE: in eliminateFrameIndex()
1594 case AMDGPU::SI_SPILL_S224_RESTORE: in eliminateFrameIndex()
1595 case AMDGPU::SI_SPILL_S192_RESTORE: in eliminateFrameIndex()
1596 case AMDGPU::SI_SPILL_S160_RESTORE: in eliminateFrameIndex()
1597 case AMDGPU::SI_SPILL_S128_RESTORE: in eliminateFrameIndex()
1598 case AMDGPU::SI_SPILL_S96_RESTORE: in eliminateFrameIndex()
1599 case AMDGPU::SI_SPILL_S64_RESTORE: in eliminateFrameIndex()
1600 case AMDGPU::SI_SPILL_S32_RESTORE: { in eliminateFrameIndex()
1606 case AMDGPU::SI_SPILL_V1024_SAVE: in eliminateFrameIndex()
1607 case AMDGPU::SI_SPILL_V512_SAVE: in eliminateFrameIndex()
1608 case AMDGPU::SI_SPILL_V256_SAVE: in eliminateFrameIndex()
1609 case AMDGPU::SI_SPILL_V224_SAVE: in eliminateFrameIndex()
1610 case AMDGPU::SI_SPILL_V192_SAVE: in eliminateFrameIndex()
1611 case AMDGPU::SI_SPILL_V160_SAVE: in eliminateFrameIndex()
1612 case AMDGPU::SI_SPILL_V128_SAVE: in eliminateFrameIndex()
1613 case AMDGPU::SI_SPILL_V96_SAVE: in eliminateFrameIndex()
1614 case AMDGPU::SI_SPILL_V64_SAVE: in eliminateFrameIndex()
1615 case AMDGPU::SI_SPILL_V32_SAVE: in eliminateFrameIndex()
1616 case AMDGPU::SI_SPILL_A1024_SAVE: in eliminateFrameIndex()
1617 case AMDGPU::SI_SPILL_A512_SAVE: in eliminateFrameIndex()
1618 case AMDGPU::SI_SPILL_A256_SAVE: in eliminateFrameIndex()
1619 case AMDGPU::SI_SPILL_A224_SAVE: in eliminateFrameIndex()
1620 case AMDGPU::SI_SPILL_A192_SAVE: in eliminateFrameIndex()
1621 case AMDGPU::SI_SPILL_A160_SAVE: in eliminateFrameIndex()
1622 case AMDGPU::SI_SPILL_A128_SAVE: in eliminateFrameIndex()
1623 case AMDGPU::SI_SPILL_A96_SAVE: in eliminateFrameIndex()
1624 case AMDGPU::SI_SPILL_A64_SAVE: in eliminateFrameIndex()
1625 case AMDGPU::SI_SPILL_A32_SAVE: { in eliminateFrameIndex()
1627 AMDGPU::OpName::vdata); in eliminateFrameIndex()
1628 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() == in eliminateFrameIndex()
1631 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR in eliminateFrameIndex()
1632 : AMDGPU::BUFFER_STORE_DWORD_OFFSET; in eliminateFrameIndex()
1636 TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), in eliminateFrameIndex()
1642 case AMDGPU::SI_SPILL_V32_RESTORE: in eliminateFrameIndex()
1643 case AMDGPU::SI_SPILL_V64_RESTORE: in eliminateFrameIndex()
1644 case AMDGPU::SI_SPILL_V96_RESTORE: in eliminateFrameIndex()
1645 case AMDGPU::SI_SPILL_V128_RESTORE: in eliminateFrameIndex()
1646 case AMDGPU::SI_SPILL_V160_RESTORE: in eliminateFrameIndex()
1647 case AMDGPU::SI_SPILL_V192_RESTORE: in eliminateFrameIndex()
1648 case AMDGPU::SI_SPILL_V224_RESTORE: in eliminateFrameIndex()
1649 case AMDGPU::SI_SPILL_V256_RESTORE: in eliminateFrameIndex()
1650 case AMDGPU::SI_SPILL_V512_RESTORE: in eliminateFrameIndex()
1651 case AMDGPU::SI_SPILL_V1024_RESTORE: in eliminateFrameIndex()
1652 case AMDGPU::SI_SPILL_A32_RESTORE: in eliminateFrameIndex()
1653 case AMDGPU::SI_SPILL_A64_RESTORE: in eliminateFrameIndex()
1654 case AMDGPU::SI_SPILL_A96_RESTORE: in eliminateFrameIndex()
1655 case AMDGPU::SI_SPILL_A128_RESTORE: in eliminateFrameIndex()
1656 case AMDGPU::SI_SPILL_A160_RESTORE: in eliminateFrameIndex()
1657 case AMDGPU::SI_SPILL_A192_RESTORE: in eliminateFrameIndex()
1658 case AMDGPU::SI_SPILL_A224_RESTORE: in eliminateFrameIndex()
1659 case AMDGPU::SI_SPILL_A256_RESTORE: in eliminateFrameIndex()
1660 case AMDGPU::SI_SPILL_A512_RESTORE: in eliminateFrameIndex()
1661 case AMDGPU::SI_SPILL_A1024_RESTORE: { in eliminateFrameIndex()
1663 AMDGPU::OpName::vdata); in eliminateFrameIndex()
1664 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() == in eliminateFrameIndex()
1667 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR in eliminateFrameIndex()
1668 : AMDGPU::BUFFER_LOAD_DWORD_OFFSET; in eliminateFrameIndex()
1672 TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), in eliminateFrameIndex()
1686 AMDGPU::getNamedOperandIdx(MI->getOpcode(), in eliminateFrameIndex()
1687 AMDGPU::OpName::saddr)); in eliminateFrameIndex()
1697 TII->getNamedOperand(*MI, AMDGPU::OpName::offset); in eliminateFrameIndex()
1707 assert(!TII->getNamedOperand(*MI, AMDGPU::OpName::vaddr) && in eliminateFrameIndex()
1714 unsigned NewOpc = AMDGPU::getFlatScratchInstSTfromSS(Opc); in eliminateFrameIndex()
1716 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr)); in eliminateFrameIndex()
1730 FIOp.ChangeToRegister(AMDGPU::M0, false); in eliminateFrameIndex()
1738 const TargetRegisterClass *RC = UseSGPR ? &AMDGPU::SReg_32_XM0RegClass in eliminateFrameIndex()
1739 : &AMDGPU::VGPR_32RegClass; in eliminateFrameIndex()
1746 unsigned Opc = UseSGPR ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in eliminateFrameIndex()
1758 : RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, in eliminateFrameIndex()
1773 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), TmpSReg) in eliminateFrameIndex()
1778 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex()
1783 BuildMI(*MBB, std::next(MI), DL, TII->get(AMDGPU::S_ADD_I32), in eliminateFrameIndex()
1799 bool IsCopy = MI->getOpcode() == AMDGPU::V_MOV_B32_e32; in eliminateFrameIndex()
1802 : RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in eliminateFrameIndex()
1807 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64), ResultReg) in eliminateFrameIndex()
1815 BuildMI(*MBB, *MIB, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64), in eliminateFrameIndex()
1820 const bool IsVOP2 = MIB->getOpcode() == AMDGPU::V_ADD_U32_e32; in eliminateFrameIndex()
1823 if (IsVOP2 || AMDGPU::isInlinableLiteral32(Offset, ST.hasInv2PiInlineImm())) { in eliminateFrameIndex()
1830 assert(MIB->getOpcode() == AMDGPU::V_ADD_CO_U32_e64 && in eliminateFrameIndex()
1836 ConstOffsetReg = getSubReg(MIB.getReg(1), AMDGPU::sub0); in eliminateFrameIndex()
1840 BuildMI(*MBB, *MIB, DL, TII->get(AMDGPU::S_MOV_B32), ConstOffsetReg) in eliminateFrameIndex()
1854 RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, false); in eliminateFrameIndex()
1857 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_LSHR_B32), ScaledReg) in eliminateFrameIndex()
1860 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), ScaledReg) in eliminateFrameIndex()
1863 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), ResultReg) in eliminateFrameIndex()
1868 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_I32), ScaledReg) in eliminateFrameIndex()
1871 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_LSHL_B32), ScaledReg) in eliminateFrameIndex()
1889 AMDGPU::getNamedOperandIdx(MI->getOpcode(), in eliminateFrameIndex()
1890 AMDGPU::OpName::vaddr)); in eliminateFrameIndex()
1892 auto &SOffset = *TII->getNamedOperand(*MI, AMDGPU::OpName::soffset); in eliminateFrameIndex()
1895 if (FrameReg != AMDGPU::NoRegister) in eliminateFrameIndex()
1900 = TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(); in eliminateFrameIndex()
1915 Register TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in eliminateFrameIndex()
1916 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex()
1931 return &AMDGPU::VReg_64RegClass; in getAnyVGPRClassForBitWidth()
1933 return &AMDGPU::VReg_96RegClass; in getAnyVGPRClassForBitWidth()
1935 return &AMDGPU::VReg_128RegClass; in getAnyVGPRClassForBitWidth()
1937 return &AMDGPU::VReg_160RegClass; in getAnyVGPRClassForBitWidth()
1939 return &AMDGPU::VReg_192RegClass; in getAnyVGPRClassForBitWidth()
1941 return &AMDGPU::VReg_224RegClass; in getAnyVGPRClassForBitWidth()
1943 return &AMDGPU::VReg_256RegClass; in getAnyVGPRClassForBitWidth()
1945 return &AMDGPU::VReg_512RegClass; in getAnyVGPRClassForBitWidth()
1947 return &AMDGPU::VReg_1024RegClass; in getAnyVGPRClassForBitWidth()
1955 return &AMDGPU::VReg_64_Align2RegClass; in getAlignedVGPRClassForBitWidth()
1957 return &AMDGPU::VReg_96_Align2RegClass; in getAlignedVGPRClassForBitWidth()
1959 return &AMDGPU::VReg_128_Align2RegClass; in getAlignedVGPRClassForBitWidth()
1961 return &AMDGPU::VReg_160_Align2RegClass; in getAlignedVGPRClassForBitWidth()
1963 return &AMDGPU::VReg_192_Align2RegClass; in getAlignedVGPRClassForBitWidth()
1965 return &AMDGPU::VReg_224_Align2RegClass; in getAlignedVGPRClassForBitWidth()
1967 return &AMDGPU::VReg_256_Align2RegClass; in getAlignedVGPRClassForBitWidth()
1969 return &AMDGPU::VReg_512_Align2RegClass; in getAlignedVGPRClassForBitWidth()
1971 return &AMDGPU::VReg_1024_Align2RegClass; in getAlignedVGPRClassForBitWidth()
1979 return &AMDGPU::VReg_1RegClass; in getVGPRClassForBitWidth()
1981 return &AMDGPU::VGPR_LO16RegClass; in getVGPRClassForBitWidth()
1983 return &AMDGPU::VGPR_32RegClass; in getVGPRClassForBitWidth()
1991 return &AMDGPU::AReg_64RegClass; in getAnyAGPRClassForBitWidth()
1993 return &AMDGPU::AReg_96RegClass; in getAnyAGPRClassForBitWidth()
1995 return &AMDGPU::AReg_128RegClass; in getAnyAGPRClassForBitWidth()
1997 return &AMDGPU::AReg_160RegClass; in getAnyAGPRClassForBitWidth()
1999 return &AMDGPU::AReg_192RegClass; in getAnyAGPRClassForBitWidth()
2001 return &AMDGPU::AReg_224RegClass; in getAnyAGPRClassForBitWidth()
2003 return &AMDGPU::AReg_256RegClass; in getAnyAGPRClassForBitWidth()
2005 return &AMDGPU::AReg_512RegClass; in getAnyAGPRClassForBitWidth()
2007 return &AMDGPU::AReg_1024RegClass; in getAnyAGPRClassForBitWidth()
2015 return &AMDGPU::AReg_64_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2017 return &AMDGPU::AReg_96_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2019 return &AMDGPU::AReg_128_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2021 return &AMDGPU::AReg_160_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2023 return &AMDGPU::AReg_192_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2025 return &AMDGPU::AReg_224_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2027 return &AMDGPU::AReg_256_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2029 return &AMDGPU::AReg_512_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2031 return &AMDGPU::AReg_1024_Align2RegClass; in getAlignedAGPRClassForBitWidth()
2039 return &AMDGPU::AGPR_LO16RegClass; in getAGPRClassForBitWidth()
2041 return &AMDGPU::AGPR_32RegClass; in getAGPRClassForBitWidth()
2049 return &AMDGPU::SGPR_LO16RegClass; in getSGPRClassForBitWidth()
2051 return &AMDGPU::SReg_32RegClass; in getSGPRClassForBitWidth()
2053 return &AMDGPU::SReg_64RegClass; in getSGPRClassForBitWidth()
2055 return &AMDGPU::SGPR_96RegClass; in getSGPRClassForBitWidth()
2057 return &AMDGPU::SGPR_128RegClass; in getSGPRClassForBitWidth()
2059 return &AMDGPU::SGPR_160RegClass; in getSGPRClassForBitWidth()
2061 return &AMDGPU::SGPR_192RegClass; in getSGPRClassForBitWidth()
2063 return &AMDGPU::SGPR_224RegClass; in getSGPRClassForBitWidth()
2065 return &AMDGPU::SGPR_256RegClass; in getSGPRClassForBitWidth()
2067 return &AMDGPU::SGPR_512RegClass; in getSGPRClassForBitWidth()
2069 return &AMDGPU::SGPR_1024RegClass; in getSGPRClassForBitWidth()
2079 &AMDGPU::VGPR_LO16RegClass, in getPhysRegClass()
2080 &AMDGPU::VGPR_HI16RegClass, in getPhysRegClass()
2081 &AMDGPU::SReg_LO16RegClass, in getPhysRegClass()
2082 &AMDGPU::AGPR_LO16RegClass, in getPhysRegClass()
2083 &AMDGPU::VGPR_32RegClass, in getPhysRegClass()
2084 &AMDGPU::SReg_32RegClass, in getPhysRegClass()
2085 &AMDGPU::AGPR_32RegClass, in getPhysRegClass()
2086 &AMDGPU::AGPR_32RegClass, in getPhysRegClass()
2087 &AMDGPU::VReg_64_Align2RegClass, in getPhysRegClass()
2088 &AMDGPU::VReg_64RegClass, in getPhysRegClass()
2089 &AMDGPU::SReg_64RegClass, in getPhysRegClass()
2090 &AMDGPU::AReg_64_Align2RegClass, in getPhysRegClass()
2091 &AMDGPU::AReg_64RegClass, in getPhysRegClass()
2092 &AMDGPU::VReg_96_Align2RegClass, in getPhysRegClass()
2093 &AMDGPU::VReg_96RegClass, in getPhysRegClass()
2094 &AMDGPU::SReg_96RegClass, in getPhysRegClass()
2095 &AMDGPU::AReg_96_Align2RegClass, in getPhysRegClass()
2096 &AMDGPU::AReg_96RegClass, in getPhysRegClass()
2097 &AMDGPU::VReg_128_Align2RegClass, in getPhysRegClass()
2098 &AMDGPU::VReg_128RegClass, in getPhysRegClass()
2099 &AMDGPU::SReg_128RegClass, in getPhysRegClass()
2100 &AMDGPU::AReg_128_Align2RegClass, in getPhysRegClass()
2101 &AMDGPU::AReg_128RegClass, in getPhysRegClass()
2102 &AMDGPU::VReg_160_Align2RegClass, in getPhysRegClass()
2103 &AMDGPU::VReg_160RegClass, in getPhysRegClass()
2104 &AMDGPU::SReg_160RegClass, in getPhysRegClass()
2105 &AMDGPU::AReg_160_Align2RegClass, in getPhysRegClass()
2106 &AMDGPU::AReg_160RegClass, in getPhysRegClass()
2107 &AMDGPU::VReg_192_Align2RegClass, in getPhysRegClass()
2108 &AMDGPU::VReg_192RegClass, in getPhysRegClass()
2109 &AMDGPU::SReg_192RegClass, in getPhysRegClass()
2110 &AMDGPU::AReg_192_Align2RegClass, in getPhysRegClass()
2111 &AMDGPU::AReg_192RegClass, in getPhysRegClass()
2112 &AMDGPU::VReg_224_Align2RegClass, in getPhysRegClass()
2113 &AMDGPU::VReg_224RegClass, in getPhysRegClass()
2114 &AMDGPU::SReg_224RegClass, in getPhysRegClass()
2115 &AMDGPU::AReg_224_Align2RegClass, in getPhysRegClass()
2116 &AMDGPU::AReg_224RegClass, in getPhysRegClass()
2117 &AMDGPU::VReg_256_Align2RegClass, in getPhysRegClass()
2118 &AMDGPU::VReg_256RegClass, in getPhysRegClass()
2119 &AMDGPU::SReg_256RegClass, in getPhysRegClass()
2120 &AMDGPU::AReg_256_Align2RegClass, in getPhysRegClass()
2121 &AMDGPU::AReg_256RegClass, in getPhysRegClass()
2122 &AMDGPU::VReg_512_Align2RegClass, in getPhysRegClass()
2123 &AMDGPU::VReg_512RegClass, in getPhysRegClass()
2124 &AMDGPU::SReg_512RegClass, in getPhysRegClass()
2125 &AMDGPU::AReg_512_Align2RegClass, in getPhysRegClass()
2126 &AMDGPU::AReg_512RegClass, in getPhysRegClass()
2127 &AMDGPU::SReg_1024RegClass, in getPhysRegClass()
2128 &AMDGPU::VReg_1024_Align2RegClass, in getPhysRegClass()
2129 &AMDGPU::VReg_1024RegClass, in getPhysRegClass()
2130 &AMDGPU::AReg_1024_Align2RegClass, in getPhysRegClass()
2131 &AMDGPU::AReg_1024RegClass, in getPhysRegClass()
2132 &AMDGPU::SCC_CLASSRegClass, in getPhysRegClass()
2133 &AMDGPU::Pseudo_SReg_32RegClass, in getPhysRegClass()
2134 &AMDGPU::Pseudo_SReg_128RegClass, in getPhysRegClass()
2160 return getCommonSubClass(&AMDGPU::VGPR_LO16RegClass, RC) != nullptr || in hasVGPRs()
2161 getCommonSubClass(&AMDGPU::VGPR_HI16RegClass, RC) != nullptr; in hasVGPRs()
2203 return &AMDGPU::SGPR_32RegClass; in getEquivalentSGPRClass()
2211 if (SubIdx == AMDGPU::NoSubRegister) in getSubRegClass()
2218 RC = &AMDGPU::SGPR_32RegClass; in getSubRegClass()
2241 if (OpType >= AMDGPU::OPERAND_REG_INLINE_AC_FIRST && in opCanUseInlineConstant()
2242 OpType <= AMDGPU::OPERAND_REG_INLINE_AC_LAST) in opCanUseInlineConstant()
2245 return OpType >= AMDGPU::OPERAND_SRC_FIRST && in opCanUseInlineConstant()
2246 OpType <= AMDGPU::OPERAND_SRC_LAST; in opCanUseInlineConstant()
2275 return OpType >= AMDGPU::OPERAND_REG_IMM_FIRST && in opCanUseLiteralConstant()
2276 OpType <= AMDGPU::OPERAND_REG_IMM_LAST; in opCanUseLiteralConstant()
2301 const unsigned RegBitWidth = AMDGPU::getRegBitWidth(*RC->MC); in getRegSplitParts()
2365 case AMDGPU::VGPR_32RegClassID: in getRegPressureLimit()
2366 case AMDGPU::VGPR_LO16RegClassID: in getRegPressureLimit()
2367 case AMDGPU::VGPR_HI16RegClassID: in getRegPressureLimit()
2369 case AMDGPU::SGPR_32RegClassID: in getRegPressureLimit()
2370 case AMDGPU::SGPR_LO16RegClassID: in getRegPressureLimit()
2377 if (Idx == AMDGPU::RegisterPressureSets::VGPR_32 || in getRegPressureSetLimit()
2378 Idx == AMDGPU::RegisterPressureSets::AGPR_32) in getRegPressureSetLimit()
2379 return getRegPressureLimit(&AMDGPU::VGPR_32RegClass, in getRegPressureSetLimit()
2382 if (Idx == AMDGPU::RegisterPressureSets::SReg_32) in getRegPressureSetLimit()
2383 return getRegPressureLimit(&AMDGPU::SGPR_32RegClass, in getRegPressureSetLimit()
2400 return AMDGPU::SGPR30_SGPR31; in getReturnAddressReg()
2408 case AMDGPU::VGPRRegBankID: in getRegClassForSizeOnBank()
2410 case AMDGPU::VCCRegBankID: in getRegClassForSizeOnBank()
2412 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getRegClassForSizeOnBank()
2413 : &AMDGPU::SReg_64_XEXECRegClass; in getRegClassForSizeOnBank()
2414 case AMDGPU::SGPRRegBankID: in getRegClassForSizeOnBank()
2416 case AMDGPU::AGPRRegBankID: in getRegClassForSizeOnBank()
2435 return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC; in getVCC()
2440 return ST.needsAlignedVGPRs() ? &AMDGPU::VReg_64_Align2RegClass in getVGPR64Class()
2441 : &AMDGPU::VReg_64RegClass; in getVGPR64Class()
2447 case AMDGPU::SReg_1RegClassID: in getRegClass()
2449 case AMDGPU::SReg_1_XEXECRegClassID: in getRegClass()
2450 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getRegClass()
2451 : &AMDGPU::SReg_64_XEXECRegClass; in getRegClass()
2517 for (const TargetRegisterClass &RC : { AMDGPU::VGPR_32RegClass, in get32BitRegister()
2518 AMDGPU::SReg_32RegClass, in get32BitRegister()
2519 AMDGPU::AGPR_32RegClass } ) { in get32BitRegister()
2520 if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::lo16, &RC)) in get32BitRegister()
2523 if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::hi16, in get32BitRegister()
2524 &AMDGPU::VGPR_32RegClass)) { in get32BitRegister()
2528 return AMDGPU::NoRegister; in get32BitRegister()
2545 case AMDGPU::SGPR_NULL: in isConstantPhysReg()
2546 case AMDGPU::SRC_SHARED_BASE: in isConstantPhysReg()
2547 case AMDGPU::SRC_PRIVATE_BASE: in isConstantPhysReg()
2548 case AMDGPU::SRC_SHARED_LIMIT: in isConstantPhysReg()
2549 case AMDGPU::SRC_PRIVATE_LIMIT: in isConstantPhysReg()
2558 return makeArrayRef(AMDGPU::SGPR_128RegClass.begin(), in getAllSGPR128()
2564 return makeArrayRef(AMDGPU::SGPR_64RegClass.begin(), in getAllSGPR64()
2570 return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(), ST.getMaxNumSGPRs(MF)); in getAllSGPR32()