92                          const MachineInstr &Sel, const MachineInstr &And) {  in isDefBetween()  argument
93   SlotIndex AndIdx = LIS->getInstructionIndex(And);  in isDefBetween()
132   auto *And =  in optimizeVcndVcmpPair()  local
134   if (!And || And->getOpcode() != AndOpc ||  in optimizeVcndVcmpPair()
135       !And->getOperand(1).isReg() || !And->getOperand(2).isReg())  in optimizeVcndVcmpPair()
138   MachineOperand *AndCC = &And->getOperand(1);  in optimizeVcndVcmpPair()
142     AndCC = &And->getOperand(2);  in optimizeVcndVcmpPair()
145   } else if (And->getOperand(2).getReg() != Register(ExecReg)) {  in optimizeVcndVcmpPair()
149   auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, *MRI, LIS);  in optimizeVcndVcmpPair()
152       Cmp->getParent() != And->getParent())  in optimizeVcndVcmpPair()
182   if (isDefBetween(*TRI, LIS, CCReg, *Sel, *And))  in optimizeVcndVcmpPair()
186                     << *And);  in optimizeVcndVcmpPair()
188   LIS->RemoveMachineInstrFromMaps(*And);  in optimizeVcndVcmpPair()
190       BuildMI(MBB, *And, And->getDebugLoc(), TII->get(Andn2Opc),  in optimizeVcndVcmpPair()
191               And->getOperand(0).getReg())  in optimizeVcndVcmpPair()
194   MachineOperand &AndSCC = And->getOperand(3);  in optimizeVcndVcmpPair()
199   And->eraseFromParent();  in optimizeVcndVcmpPair()