Lines Matching refs:AMDGPU
57 case AMDGPU::COPY: in isCopyFromExec()
58 case AMDGPU::S_MOV_B64: in isCopyFromExec()
59 case AMDGPU::S_MOV_B64_term: in isCopyFromExec()
60 case AMDGPU::S_MOV_B32: in isCopyFromExec()
61 case AMDGPU::S_MOV_B32_term: { in isCopyFromExec()
64 Src.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC)) in isCopyFromExec()
69 return AMDGPU::NoRegister; in isCopyFromExec()
75 case AMDGPU::COPY: in isCopyToExec()
76 case AMDGPU::S_MOV_B64: in isCopyToExec()
77 case AMDGPU::S_MOV_B32: { in isCopyToExec()
80 Dst.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC) && in isCopyToExec()
85 case AMDGPU::S_MOV_B64_term: in isCopyToExec()
86 case AMDGPU::S_MOV_B32_term: in isCopyToExec()
97 case AMDGPU::S_AND_B64: in isLogicalOpOnExec()
98 case AMDGPU::S_OR_B64: in isLogicalOpOnExec()
99 case AMDGPU::S_XOR_B64: in isLogicalOpOnExec()
100 case AMDGPU::S_ANDN2_B64: in isLogicalOpOnExec()
101 case AMDGPU::S_ORN2_B64: in isLogicalOpOnExec()
102 case AMDGPU::S_NAND_B64: in isLogicalOpOnExec()
103 case AMDGPU::S_NOR_B64: in isLogicalOpOnExec()
104 case AMDGPU::S_XNOR_B64: { in isLogicalOpOnExec()
106 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
109 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
113 case AMDGPU::S_AND_B32: in isLogicalOpOnExec()
114 case AMDGPU::S_OR_B32: in isLogicalOpOnExec()
115 case AMDGPU::S_XOR_B32: in isLogicalOpOnExec()
116 case AMDGPU::S_ANDN2_B32: in isLogicalOpOnExec()
117 case AMDGPU::S_ORN2_B32: in isLogicalOpOnExec()
118 case AMDGPU::S_NAND_B32: in isLogicalOpOnExec()
119 case AMDGPU::S_NOR_B32: in isLogicalOpOnExec()
120 case AMDGPU::S_XNOR_B32: { in isLogicalOpOnExec()
122 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
125 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
131 return AMDGPU::NoRegister; in isLogicalOpOnExec()
136 case AMDGPU::S_AND_B64: in getSaveExecOp()
137 return AMDGPU::S_AND_SAVEEXEC_B64; in getSaveExecOp()
138 case AMDGPU::S_OR_B64: in getSaveExecOp()
139 return AMDGPU::S_OR_SAVEEXEC_B64; in getSaveExecOp()
140 case AMDGPU::S_XOR_B64: in getSaveExecOp()
141 return AMDGPU::S_XOR_SAVEEXEC_B64; in getSaveExecOp()
142 case AMDGPU::S_ANDN2_B64: in getSaveExecOp()
143 return AMDGPU::S_ANDN2_SAVEEXEC_B64; in getSaveExecOp()
144 case AMDGPU::S_ORN2_B64: in getSaveExecOp()
145 return AMDGPU::S_ORN2_SAVEEXEC_B64; in getSaveExecOp()
146 case AMDGPU::S_NAND_B64: in getSaveExecOp()
147 return AMDGPU::S_NAND_SAVEEXEC_B64; in getSaveExecOp()
148 case AMDGPU::S_NOR_B64: in getSaveExecOp()
149 return AMDGPU::S_NOR_SAVEEXEC_B64; in getSaveExecOp()
150 case AMDGPU::S_XNOR_B64: in getSaveExecOp()
151 return AMDGPU::S_XNOR_SAVEEXEC_B64; in getSaveExecOp()
152 case AMDGPU::S_AND_B32: in getSaveExecOp()
153 return AMDGPU::S_AND_SAVEEXEC_B32; in getSaveExecOp()
154 case AMDGPU::S_OR_B32: in getSaveExecOp()
155 return AMDGPU::S_OR_SAVEEXEC_B32; in getSaveExecOp()
156 case AMDGPU::S_XOR_B32: in getSaveExecOp()
157 return AMDGPU::S_XOR_SAVEEXEC_B32; in getSaveExecOp()
158 case AMDGPU::S_ANDN2_B32: in getSaveExecOp()
159 return AMDGPU::S_ANDN2_SAVEEXEC_B32; in getSaveExecOp()
160 case AMDGPU::S_ORN2_B32: in getSaveExecOp()
161 return AMDGPU::S_ORN2_SAVEEXEC_B32; in getSaveExecOp()
162 case AMDGPU::S_NAND_B32: in getSaveExecOp()
163 return AMDGPU::S_NAND_SAVEEXEC_B32; in getSaveExecOp()
164 case AMDGPU::S_NOR_B32: in getSaveExecOp()
165 return AMDGPU::S_NOR_SAVEEXEC_B32; in getSaveExecOp()
166 case AMDGPU::S_XNOR_B32: in getSaveExecOp()
167 return AMDGPU::S_XNOR_SAVEEXEC_B32; in getSaveExecOp()
169 return AMDGPU::INSTRUCTION_LIST_END; in getSaveExecOp()
177 case AMDGPU::S_MOV_B32_term: { in removeTerminatorBit()
179 MI.setDesc(TII.get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B32)); in removeTerminatorBit()
182 case AMDGPU::S_MOV_B64_term: { in removeTerminatorBit()
184 MI.setDesc(TII.get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B64)); in removeTerminatorBit()
187 case AMDGPU::S_XOR_B64_term: { in removeTerminatorBit()
190 MI.setDesc(TII.get(AMDGPU::S_XOR_B64)); in removeTerminatorBit()
193 case AMDGPU::S_XOR_B32_term: { in removeTerminatorBit()
196 MI.setDesc(TII.get(AMDGPU::S_XOR_B32)); in removeTerminatorBit()
199 case AMDGPU::S_OR_B64_term: { in removeTerminatorBit()
202 MI.setDesc(TII.get(AMDGPU::S_OR_B64)); in removeTerminatorBit()
205 case AMDGPU::S_OR_B32_term: { in removeTerminatorBit()
208 MI.setDesc(TII.get(AMDGPU::S_OR_B32)); in removeTerminatorBit()
211 case AMDGPU::S_ANDN2_B64_term: { in removeTerminatorBit()
214 MI.setDesc(TII.get(AMDGPU::S_ANDN2_B64)); in removeTerminatorBit()
217 case AMDGPU::S_ANDN2_B32_term: { in removeTerminatorBit()
220 MI.setDesc(TII.get(AMDGPU::S_ANDN2_B32)); in removeTerminatorBit()
223 case AMDGPU::S_AND_B64_term: { in removeTerminatorBit()
226 MI.setDesc(TII.get(AMDGPU::S_AND_B64)); in removeTerminatorBit()
229 case AMDGPU::S_AND_B32_term: { in removeTerminatorBit()
232 MI.setDesc(TII.get(AMDGPU::S_AND_B32)); in removeTerminatorBit()
302 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
391 if (SaveExecOp == AMDGPU::INSTRUCTION_LIST_END) in runOnMachineFunction()
457 AMDGPU::NoSubRegister, *TRI); in runOnMachineFunction()