217   void reportUnsupported(const MachineBasicBlock::iterator &MI,
233       const MachineBasicBlock::iterator &MI) const;
242       const MachineBasicBlock::iterator &MI) const;
246       const MachineBasicBlock::iterator &MI) const;
251       const MachineBasicBlock::iterator &MI) const;
256       const MachineBasicBlock::iterator &MI) const;
277   bool enableNamedBit(const MachineBasicBlock::iterator MI,
288   virtual bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
295   virtual bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
302   virtual bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
309   virtual bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
321   virtual bool insertWait(MachineBasicBlock::iterator &MI,
333   virtual bool insertAcquire(MachineBasicBlock::iterator &MI,
344   virtual bool insertRelease(MachineBasicBlock::iterator &MI,
360   bool enableGLCBit(const MachineBasicBlock::iterator &MI) const {  in enableGLCBit()
366   bool enableSLCBit(const MachineBasicBlock::iterator &MI) const {  in enableSLCBit()
374   bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
378   bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
382   bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
386   bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
391   bool insertWait(MachineBasicBlock::iterator &MI,
398   bool insertAcquire(MachineBasicBlock::iterator &MI,
403   bool insertRelease(MachineBasicBlock::iterator &MI,
415   bool insertAcquire(MachineBasicBlock::iterator &MI,
427   bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
431   bool enableStoreCacheBypass(const MachineBasicBlock::iterator &MI,
435   bool enableRMWCacheBypass(const MachineBasicBlock::iterator &MI,
439   bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
444   bool insertWait(MachineBasicBlock::iterator &MI,
451   bool insertAcquire(MachineBasicBlock::iterator &MI,
456   bool insertRelease(MachineBasicBlock::iterator &MI,
468   bool enableDLCBit(const MachineBasicBlock::iterator &MI) const {  in enableDLCBit()
476   bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
480   bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
485   bool insertWait(MachineBasicBlock::iterator &MI,
492   bool insertAcquire(MachineBasicBlock::iterator &MI,
505   std::list<MachineBasicBlock::iterator> AtomicPseudoMIs;
520                   MachineBasicBlock::iterator &MI);
524                    MachineBasicBlock::iterator &MI);
528                          MachineBasicBlock::iterator &MI);
532                                 MachineBasicBlock::iterator &MI);
553 void SIMemOpAccess::reportUnsupported(const MachineBasicBlock::iterator &MI,  in reportUnsupported()
626     const MachineBasicBlock::iterator &MI) const {  in constructFromMIWithMMO()
689     const MachineBasicBlock::iterator &MI) const {  in getLoadInfo()
703     const MachineBasicBlock::iterator &MI) const {  in getStoreInfo()
717     const MachineBasicBlock::iterator &MI) const {  in getAtomicFenceInfo()
750     const MachineBasicBlock::iterator &MI) const {  in getAtomicCmpxchgOrRmwInfo()
769 bool SICacheControl::enableNamedBit(const MachineBasicBlock::iterator MI,  in enableNamedBit()
792     const MachineBasicBlock::iterator &MI,  in enableLoadCacheBypass()
825     const MachineBasicBlock::iterator &MI,  in enableStoreCacheBypass()
838     const MachineBasicBlock::iterator &MI,  in enableRMWCacheBypass()
851     MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op,  in enableVolatileAndOrNonTemporal()
891 bool SIGfx6CacheControl::insertWait(MachineBasicBlock::iterator &MI,  in insertWait()
988 bool SIGfx6CacheControl::insertAcquire(MachineBasicBlock::iterator &MI,  in insertAcquire()
1033 bool SIGfx6CacheControl::insertRelease(MachineBasicBlock::iterator &MI,  in insertRelease()
1042 bool SIGfx7CacheControl::insertAcquire(MachineBasicBlock::iterator &MI,  in insertAcquire()
1094     const MachineBasicBlock::iterator &MI,  in enableLoadCacheBypass()
1133     const MachineBasicBlock::iterator &MI,  in enableStoreCacheBypass()
1168     const MachineBasicBlock::iterator &MI,  in enableRMWCacheBypass()
1196     MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op,  in enableVolatileAndOrNonTemporal()
1237 bool SIGfx90ACacheControl::insertWait(MachineBasicBlock::iterator &MI,  in insertWait()
1265 bool SIGfx90ACacheControl::insertAcquire(MachineBasicBlock::iterator &MI,  in insertAcquire()
1331 bool SIGfx90ACacheControl::insertRelease(MachineBasicBlock::iterator &MI,  in insertRelease()
1380     const MachineBasicBlock::iterator &MI,  in enableLoadCacheBypass()
1423     MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op,  in enableVolatileAndOrNonTemporal()
1465 bool SIGfx10CacheControl::insertWait(MachineBasicBlock::iterator &MI,  in insertWait()
1585 bool SIGfx10CacheControl::insertAcquire(MachineBasicBlock::iterator &MI,  in insertAcquire()
1652                                    MachineBasicBlock::iterator &MI) {  in expandLoad()
1697                                     MachineBasicBlock::iterator &MI) {  in expandStore()
1730                                           MachineBasicBlock::iterator &MI) {  in expandAtomicFence()
1772   MachineBasicBlock::iterator &MI) {  in expandAtomicCmpxchgOrRmw()