43   LOAD = 1u << 0,  enumerator
862   assert( Op == SIMemOp::LOAD || Op == SIMemOp::STORE);  in enableVolatileAndOrNonTemporal()
867     if (Op == SIMemOp::LOAD)  in enableVolatileAndOrNonTemporal()
1038     return insertWait(MI, Scope, AddrSpace, SIMemOp::LOAD | SIMemOp::STORE,  in insertRelease()
1207   assert( Op == SIMemOp::LOAD || Op == SIMemOp::STORE);  in enableVolatileAndOrNonTemporal()
1212     if (Op == SIMemOp::LOAD) {  in enableVolatileAndOrNonTemporal()
1435   assert( Op == SIMemOp::LOAD || Op == SIMemOp::STORE);  in enableVolatileAndOrNonTemporal()
1441     if (Op == SIMemOp::LOAD) {  in enableVolatileAndOrNonTemporal()
1488       if ((Op & SIMemOp::LOAD) != SIMemOp::NONE)  in insertWait()
1500         if ((Op & SIMemOp::LOAD) != SIMemOp::NONE)  in insertWait()
1668                                 SIMemOp::LOAD | SIMemOp::STORE,  in expandLoad()
1676                                 SIMemOp::LOAD,  in expandLoad()
1691                                                 SIMemOp::LOAD, MOI.isVolatile(),  in expandLoad()
1803                                 isAtomicRet(*MI) ? SIMemOp::LOAD :  in expandAtomicCmpxchgOrRmw()