102     unsigned Width;  member
528   Width = getOpcodeWidth(*I, TII);  in setMI()
777     if (getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, STI) == 0)  in offsetsCanBeCombined()
788     return (EltOffset0 + CI.Width == EltOffset1 ||  in offsetsCanBeCombined()
789             EltOffset1 + Paired.Width == EltOffset0) &&  in offsetsCanBeCombined()
856   const unsigned Width = (CI.Width + Paired.Width);  in widthsFit()  local
859     return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3));  in widthsFit()
861     switch (Width) {  in widthsFit()
1401       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);  in mergeTBufferLoadPair()
1479       getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM);  in mergeTBufferStorePair()
1509   const unsigned Width = CI.Width + Paired.Width;  in getNewOpcode()  local
1516                                   Width);  in getNewOpcode()
1520                                   Width);  in getNewOpcode()
1525     switch (Width) {  in getNewOpcode()
1534     assert("No overlaps" && (countPopulation(CI.DMask | Paired.DMask) == Width));  in getNewOpcode()
1535     return AMDGPU::getMaskedMIMGOp(CI.I->getOpcode(), Width);  in getNewOpcode()
1542   if (CI.Width == 0 || Paired.Width == 0 || CI.Width + Paired.Width > 4)  in getSubRegIdxs()
1547     assert((countPopulation(CI.DMask | Paired.DMask) == CI.Width + Paired.Width) &&  in getSubRegIdxs()
1562   assert(CI.Width >= 1 && CI.Width <= 3);  in getSubRegIdxs()
1563   assert(Paired.Width >= 1 && Paired.Width <= 3);  in getSubRegIdxs()
1566     Idx1 = Idxs[0][Paired.Width - 1];  in getSubRegIdxs()
1567     Idx0 = Idxs[Paired.Width][CI.Width - 1];  in getSubRegIdxs()
1569     Idx0 = Idxs[0][CI.Width - 1];  in getSubRegIdxs()
1570     Idx1 = Idxs[CI.Width][Paired.Width - 1];  in getSubRegIdxs()
1580     switch (CI.Width + Paired.Width) {  in getTargetRegisterClass()
1594   unsigned BitWidth = 32 * (CI.Width + Paired.Width);  in getTargetRegisterClass()
2143       OptimizeListAgain |= (CI.Width + Paired.Width) < 16;  in optimizeInstsWithSameBaseAddr()
2150       OptimizeListAgain |= (CI.Width + Paired.Width) < 4;  in optimizeInstsWithSameBaseAddr()
2157       OptimizeListAgain |= (CI.Width + Paired.Width) < 4;  in optimizeInstsWithSameBaseAddr()
2164       OptimizeListAgain |= (CI.Width + Paired.Width) < 4;  in optimizeInstsWithSameBaseAddr()
2171       OptimizeListAgain |= (CI.Width + Paired.Width) < 4;  in optimizeInstsWithSameBaseAddr()
2178       OptimizeListAgain |= (CI.Width + Paired.Width) < 4;  in optimizeInstsWithSameBaseAddr()