Lines Matching refs:STM

162                const GCNSubtarget &STM);
181 const GCNSubtarget *STM = nullptr; member in __anon8de982330111::SILoadStoreOptimizer
489 const GCNSubtarget &STM) { in setMI() argument
509 EltSize = AMDGPU::convertSMRDOffsetUnits(STM, 4); in setMI()
853 bool SILoadStoreOptimizer::widthsFit(const GCNSubtarget &STM, in widthsFit() argument
859 return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3)); in widthsFit()
902 (!widthsFit(*STM, CI, Paired) || !offsetsCanBeCombined(CI, *STM, Paired))) in checkAndPrepareMerge()
1015 offsetsCanBeCombined(CI, *STM, Paired, true); in checkAndPrepareMerge()
1034 if (STM->ldsRequiresM0Init()) in read2Opcode()
1040 if (STM->ldsRequiresM0Init()) in read2ST64Opcode()
1131 if (STM->ldsRequiresM0Init()) in write2Opcode()
1138 if (STM->ldsRequiresM0Init()) in write2ST64Opcode()
1401 getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM); in mergeTBufferLoadPair()
1479 getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM); in mergeTBufferStorePair()
1899 static_cast<const SITargetLowering *>(STM->getTargetLowering()); in promoteConstantOffsetToImm()
2017 CI.setMI(MI, *TII, *STM); in collectMergeableInsts()
2130 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2136 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2142 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2149 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2156 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2163 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2170 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2177 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2196 STM = &MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
2197 if (!STM->loadStoreOptEnabled()) in runOnMachineFunction()
2200 TII = STM->getInstrInfo(); in runOnMachineFunction()