Lines Matching refs:CI
188 static bool dmasksCanBeCombined(const CombineInfo &CI,
191 static bool offsetsCanBeCombined(CombineInfo &CI, const GCNSubtarget &STI,
193 static bool widthsFit(const GCNSubtarget &STI, const CombineInfo &CI,
195 static unsigned getNewOpcode(const CombineInfo &CI, const CombineInfo &Paired);
196 static std::pair<unsigned, unsigned> getSubRegIdxs(const CombineInfo &CI,
198 const TargetRegisterClass *getTargetRegisterClass(const CombineInfo &CI,
202 bool checkAndPrepareMerge(CombineInfo &CI, CombineInfo &Paired,
207 MachineBasicBlock::iterator mergeRead2Pair(CombineInfo &CI,
214 mergeWrite2Pair(CombineInfo &CI, CombineInfo &Paired,
217 mergeImagePair(CombineInfo &CI, CombineInfo &Paired,
220 mergeSBufferLoadImmPair(CombineInfo &CI, CombineInfo &Paired,
223 mergeBufferLoadPair(CombineInfo &CI, CombineInfo &Paired,
226 mergeBufferStorePair(CombineInfo &CI, CombineInfo &Paired,
229 mergeTBufferLoadPair(CombineInfo &CI, CombineInfo &Paired,
232 mergeTBufferStorePair(CombineInfo &CI, CombineInfo &Paired,
244 bool promoteConstantOffsetToImm(MachineInstr &CI,
247 void addInstToMergeableList(const CombineInfo &CI,
670 bool SILoadStoreOptimizer::dmasksCanBeCombined(const CombineInfo &CI, in dmasksCanBeCombined() argument
673 assert(CI.InstClass == MIMG); in dmasksCanBeCombined()
676 const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe); in dmasksCanBeCombined()
677 const auto *LWEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::lwe); in dmasksCanBeCombined()
688 int Idx = AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), op); in dmasksCanBeCombined()
692 CI.I->getOperand(Idx).getImm() != Paired.I->getOperand(Idx).getImm()) in dmasksCanBeCombined()
697 unsigned MaxMask = std::max(CI.DMask, Paired.DMask); in dmasksCanBeCombined()
698 unsigned MinMask = std::min(CI.DMask, Paired.DMask); in dmasksCanBeCombined()
742 bool SILoadStoreOptimizer::offsetsCanBeCombined(CombineInfo &CI, in offsetsCanBeCombined() argument
746 assert(CI.InstClass != MIMG); in offsetsCanBeCombined()
750 if (CI.Offset == Paired.Offset) in offsetsCanBeCombined()
754 if ((CI.Offset % CI.EltSize != 0) || (Paired.Offset % CI.EltSize != 0)) in offsetsCanBeCombined()
757 if (CI.InstClass == TBUFFER_LOAD || CI.InstClass == TBUFFER_STORE) { in offsetsCanBeCombined()
760 llvm::AMDGPU::getGcnBufferFormatInfo(CI.Format, STI); in offsetsCanBeCombined()
777 if (getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, STI) == 0) in offsetsCanBeCombined()
781 uint32_t EltOffset0 = CI.Offset / CI.EltSize; in offsetsCanBeCombined()
782 uint32_t EltOffset1 = Paired.Offset / CI.EltSize; in offsetsCanBeCombined()
783 CI.UseST64 = false; in offsetsCanBeCombined()
784 CI.BaseOff = 0; in offsetsCanBeCombined()
787 if ((CI.InstClass != DS_READ) && (CI.InstClass != DS_WRITE)) { in offsetsCanBeCombined()
788 return (EltOffset0 + CI.Width == EltOffset1 || in offsetsCanBeCombined()
790 CI.CPol == Paired.CPol && in offsetsCanBeCombined()
791 (CI.InstClass == S_BUFFER_LOAD_IMM || CI.CPol == Paired.CPol); in offsetsCanBeCombined()
799 CI.Offset = EltOffset0 / 64; in offsetsCanBeCombined()
801 CI.UseST64 = true; in offsetsCanBeCombined()
809 CI.Offset = EltOffset0; in offsetsCanBeCombined()
829 CI.BaseOff = BaseOff * CI.EltSize; in offsetsCanBeCombined()
830 CI.Offset = (EltOffset0 - BaseOff) / 64; in offsetsCanBeCombined()
832 CI.UseST64 = true; in offsetsCanBeCombined()
843 CI.BaseOff = BaseOff * CI.EltSize; in offsetsCanBeCombined()
844 CI.Offset = EltOffset0 - BaseOff; in offsetsCanBeCombined()
854 const CombineInfo &CI, in widthsFit() argument
856 const unsigned Width = (CI.Width + Paired.Width); in widthsFit()
857 switch (CI.InstClass) { in widthsFit()
893 CombineInfo &CI, CombineInfo &Paired, in checkAndPrepareMerge() argument
898 if (CI.InstClass == MIMG && !dmasksCanBeCombined(CI, *TII, Paired)) in checkAndPrepareMerge()
901 if (CI.InstClass != MIMG && in checkAndPrepareMerge()
902 (!widthsFit(*STM, CI, Paired) || !offsetsCanBeCombined(CI, *STM, Paired))) in checkAndPrepareMerge()
905 const unsigned Opc = CI.I->getOpcode(); in checkAndPrepareMerge()
915 AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AMDGPU::OpName::swz); in checkAndPrepareMerge()
916 if (Swizzled != -1 && CI.I->getOperand(Swizzled).getImm()) in checkAndPrepareMerge()
921 addDefsUsesToList(*CI.I, RegDefsToMove, PhysRegUsesToMove); in checkAndPrepareMerge()
923 const TargetRegisterClass *DataRC = getDataRegClass(*CI.I); in checkAndPrepareMerge()
927 MachineBasicBlock::iterator MBBI = std::next(CI.I); in checkAndPrepareMerge()
928 MachineBasicBlock::iterator MBBE = CI.I->getParent()->end(); in checkAndPrepareMerge()
956 (!memAccessesCanBeReordered(*CI.I, *MBBI, AA) || in checkAndPrepareMerge()
1002 if (IsAGPR && CI.InstClass == DS_WRITE) in checkAndPrepareMerge()
1014 if (CI.InstClass != MIMG) in checkAndPrepareMerge()
1015 offsetsCanBeCombined(CI, *STM, Paired, true); in checkAndPrepareMerge()
1026 if (!memAccessesCanBeReordered(*CI.I, *MBBI, AA) || in checkAndPrepareMerge()
1048 SILoadStoreOptimizer::mergeRead2Pair(CombineInfo &CI, CombineInfo &Paired, in mergeRead2Pair() argument
1050 MachineBasicBlock *MBB = CI.I->getParent(); in mergeRead2Pair()
1054 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeRead2Pair()
1056 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdst); in mergeRead2Pair()
1059 unsigned NewOffset0 = CI.Offset; in mergeRead2Pair()
1062 CI.UseST64 ? read2ST64Opcode(CI.EltSize) : read2Opcode(CI.EltSize); in mergeRead2Pair()
1064 unsigned SubRegIdx0 = (CI.EltSize == 4) ? AMDGPU::sub0 : AMDGPU::sub0_sub1; in mergeRead2Pair()
1065 unsigned SubRegIdx1 = (CI.EltSize == 4) ? AMDGPU::sub1 : AMDGPU::sub2_sub3; in mergeRead2Pair()
1078 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeRead2Pair()
1081 DebugLoc DL = CI.I->getDebugLoc(); in mergeRead2Pair()
1086 if (CI.BaseOff) { in mergeRead2Pair()
1089 .addImm(CI.BaseOff); in mergeRead2Pair()
1107 .cloneMergedMemRefs({&*CI.I, &*Paired.I}); in mergeRead2Pair()
1123 CI.I->eraseFromParent(); in mergeRead2Pair()
1147 SILoadStoreOptimizer::mergeWrite2Pair(CombineInfo &CI, CombineInfo &Paired, in mergeWrite2Pair() argument
1149 MachineBasicBlock *MBB = CI.I->getParent(); in mergeWrite2Pair()
1154 TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeWrite2Pair()
1156 TII->getNamedOperand(*CI.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
1160 unsigned NewOffset0 = CI.Offset; in mergeWrite2Pair()
1163 CI.UseST64 ? write2ST64Opcode(CI.EltSize) : write2Opcode(CI.EltSize); in mergeWrite2Pair()
1175 DebugLoc DL = CI.I->getDebugLoc(); in mergeWrite2Pair()
1180 if (CI.BaseOff) { in mergeWrite2Pair()
1183 .addImm(CI.BaseOff); in mergeWrite2Pair()
1203 .cloneMergedMemRefs({&*CI.I, &*Paired.I}); in mergeWrite2Pair()
1207 CI.I->eraseFromParent(); in mergeWrite2Pair()
1215 SILoadStoreOptimizer::mergeImagePair(CombineInfo &CI, CombineInfo &Paired, in mergeImagePair() argument
1217 MachineBasicBlock *MBB = CI.I->getParent(); in mergeImagePair()
1218 DebugLoc DL = CI.I->getDebugLoc(); in mergeImagePair()
1219 const unsigned Opcode = getNewOpcode(CI, Paired); in mergeImagePair()
1221 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeImagePair()
1224 unsigned MergedDMask = CI.DMask | Paired.DMask; in mergeImagePair()
1226 AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AMDGPU::OpName::dmask); in mergeImagePair()
1229 for (unsigned I = 1, E = (*CI.I).getNumOperands(); I != E; ++I) { in mergeImagePair()
1233 MIB.add((*CI.I).getOperand(I)); in mergeImagePair()
1239 assert(CI.I->hasOneMemOperand() && Paired.I->hasOneMemOperand()); in mergeImagePair()
1241 const MachineMemOperand *MMOa = *CI.I->memoperands_begin(); in mergeImagePair()
1247 std::tie(SubRegIdx0, SubRegIdx1) = getSubRegIdxs(CI, Paired); in mergeImagePair()
1251 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeImagePair()
1263 CI.I->eraseFromParent(); in mergeImagePair()
1269 CombineInfo &CI, CombineInfo &Paired, in mergeSBufferLoadImmPair() argument
1271 MachineBasicBlock *MBB = CI.I->getParent(); in mergeSBufferLoadImmPair()
1272 DebugLoc DL = CI.I->getDebugLoc(); in mergeSBufferLoadImmPair()
1273 const unsigned Opcode = getNewOpcode(CI, Paired); in mergeSBufferLoadImmPair()
1275 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeSBufferLoadImmPair()
1278 unsigned MergedOffset = std::min(CI.Offset, Paired.Offset); in mergeSBufferLoadImmPair()
1283 assert(CI.I->hasOneMemOperand() && Paired.I->hasOneMemOperand()); in mergeSBufferLoadImmPair()
1285 const MachineMemOperand *MMOa = *CI.I->memoperands_begin(); in mergeSBufferLoadImmPair()
1290 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::sbase)) in mergeSBufferLoadImmPair()
1292 .addImm(CI.CPol) // cpol in mergeSBufferLoadImmPair()
1295 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeSBufferLoadImmPair()
1301 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::sdst); in mergeSBufferLoadImmPair()
1313 CI.I->eraseFromParent(); in mergeSBufferLoadImmPair()
1319 CombineInfo &CI, CombineInfo &Paired, in mergeBufferLoadPair() argument
1321 MachineBasicBlock *MBB = CI.I->getParent(); in mergeBufferLoadPair()
1322 DebugLoc DL = CI.I->getDebugLoc(); in mergeBufferLoadPair()
1324 const unsigned Opcode = getNewOpcode(CI, Paired); in mergeBufferLoadPair()
1326 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeBufferLoadPair()
1330 unsigned MergedOffset = std::min(CI.Offset, Paired.Offset); in mergeBufferLoadPair()
1337 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeBufferLoadPair()
1342 assert(CI.I->hasOneMemOperand() && Paired.I->hasOneMemOperand()); in mergeBufferLoadPair()
1344 const MachineMemOperand *MMOa = *CI.I->memoperands_begin(); in mergeBufferLoadPair()
1348 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferLoadPair()
1349 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferLoadPair()
1351 .addImm(CI.CPol) // cpol in mergeBufferLoadPair()
1356 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeBufferLoadPair()
1362 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferLoadPair()
1374 CI.I->eraseFromParent(); in mergeBufferLoadPair()
1380 CombineInfo &CI, CombineInfo &Paired, in mergeTBufferLoadPair() argument
1382 MachineBasicBlock *MBB = CI.I->getParent(); in mergeTBufferLoadPair()
1383 DebugLoc DL = CI.I->getDebugLoc(); in mergeTBufferLoadPair()
1385 const unsigned Opcode = getNewOpcode(CI, Paired); in mergeTBufferLoadPair()
1387 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeTBufferLoadPair()
1391 unsigned MergedOffset = std::min(CI.Offset, Paired.Offset); in mergeTBufferLoadPair()
1398 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeTBufferLoadPair()
1401 getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM); in mergeTBufferLoadPair()
1406 assert(CI.I->hasOneMemOperand() && Paired.I->hasOneMemOperand()); in mergeTBufferLoadPair()
1408 const MachineMemOperand *MMOa = *CI.I->memoperands_begin(); in mergeTBufferLoadPair()
1412 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeTBufferLoadPair()
1413 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeTBufferLoadPair()
1416 .addImm(CI.CPol) // cpol in mergeTBufferLoadPair()
1422 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeTBufferLoadPair()
1428 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeTBufferLoadPair()
1440 CI.I->eraseFromParent(); in mergeTBufferLoadPair()
1446 CombineInfo &CI, CombineInfo &Paired, in mergeTBufferStorePair() argument
1448 MachineBasicBlock *MBB = CI.I->getParent(); in mergeTBufferStorePair()
1449 DebugLoc DL = CI.I->getDebugLoc(); in mergeTBufferStorePair()
1451 const unsigned Opcode = getNewOpcode(CI, Paired); in mergeTBufferStorePair()
1453 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeTBufferStorePair()
1458 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeTBufferStorePair()
1461 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeTBufferStorePair()
1476 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeTBufferStorePair()
1479 getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM); in mergeTBufferStorePair()
1484 assert(CI.I->hasOneMemOperand() && Paired.I->hasOneMemOperand()); in mergeTBufferStorePair()
1486 const MachineMemOperand *MMOa = *CI.I->memoperands_begin(); in mergeTBufferStorePair()
1490 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeTBufferStorePair()
1491 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeTBufferStorePair()
1492 .addImm(std::min(CI.Offset, Paired.Offset)) // offset in mergeTBufferStorePair()
1494 .addImm(CI.CPol) // cpol in mergeTBufferStorePair()
1502 CI.I->eraseFromParent(); in mergeTBufferStorePair()
1507 unsigned SILoadStoreOptimizer::getNewOpcode(const CombineInfo &CI, in getNewOpcode() argument
1509 const unsigned Width = CI.Width + Paired.Width; in getNewOpcode()
1511 switch (CI.InstClass) { in getNewOpcode()
1513 assert(CI.InstClass == BUFFER_LOAD || CI.InstClass == BUFFER_STORE); in getNewOpcode()
1515 return AMDGPU::getMUBUFOpcode(AMDGPU::getMUBUFBaseOpcode(CI.I->getOpcode()), in getNewOpcode()
1519 return AMDGPU::getMTBUFOpcode(AMDGPU::getMTBUFBaseOpcode(CI.I->getOpcode()), in getNewOpcode()
1534 assert("No overlaps" && (countPopulation(CI.DMask | Paired.DMask) == Width)); in getNewOpcode()
1535 return AMDGPU::getMaskedMIMGOp(CI.I->getOpcode(), Width); in getNewOpcode()
1540 SILoadStoreOptimizer::getSubRegIdxs(const CombineInfo &CI, const CombineInfo &Paired) { in getSubRegIdxs() argument
1542 if (CI.Width == 0 || Paired.Width == 0 || CI.Width + Paired.Width > 4) in getSubRegIdxs()
1546 if (CI.InstClass == MIMG) { in getSubRegIdxs()
1547 assert((countPopulation(CI.DMask | Paired.DMask) == CI.Width + Paired.Width) && in getSubRegIdxs()
1549 ReverseOrder = CI.DMask > Paired.DMask; in getSubRegIdxs()
1551 ReverseOrder = CI.Offset > Paired.Offset; in getSubRegIdxs()
1562 assert(CI.Width >= 1 && CI.Width <= 3); in getSubRegIdxs()
1567 Idx0 = Idxs[Paired.Width][CI.Width - 1]; in getSubRegIdxs()
1569 Idx0 = Idxs[0][CI.Width - 1]; in getSubRegIdxs()
1570 Idx1 = Idxs[CI.Width][Paired.Width - 1]; in getSubRegIdxs()
1577 SILoadStoreOptimizer::getTargetRegisterClass(const CombineInfo &CI, in getTargetRegisterClass() argument
1579 if (CI.InstClass == S_BUFFER_LOAD_IMM) { in getTargetRegisterClass()
1580 switch (CI.Width + Paired.Width) { in getTargetRegisterClass()
1594 unsigned BitWidth = 32 * (CI.Width + Paired.Width); in getTargetRegisterClass()
1595 return TRI->hasAGPRs(getDataRegClass(*CI.I)) in getTargetRegisterClass()
1601 CombineInfo &CI, CombineInfo &Paired, in mergeBufferStorePair() argument
1603 MachineBasicBlock *MBB = CI.I->getParent(); in mergeBufferStorePair()
1604 DebugLoc DL = CI.I->getDebugLoc(); in mergeBufferStorePair()
1606 const unsigned Opcode = getNewOpcode(CI, Paired); in mergeBufferStorePair()
1608 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeBufferStorePair()
1613 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeBufferStorePair()
1616 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferStorePair()
1631 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeBufferStorePair()
1637 assert(CI.I->hasOneMemOperand() && Paired.I->hasOneMemOperand()); in mergeBufferStorePair()
1639 const MachineMemOperand *MMOa = *CI.I->memoperands_begin(); in mergeBufferStorePair()
1643 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferStorePair()
1644 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferStorePair()
1645 .addImm(std::min(CI.Offset, Paired.Offset)) // offset in mergeBufferStorePair()
1646 .addImm(CI.CPol) // cpol in mergeBufferStorePair()
1653 CI.I->eraseFromParent(); in mergeBufferStorePair()
1970 void SILoadStoreOptimizer::addInstToMergeableList(const CombineInfo &CI, in addInstToMergeableList() argument
1973 if (AddrList.front().InstClass == CI.InstClass && in addInstToMergeableList()
1974 AddrList.front().hasSameBaseAddress(*CI.I)) { in addInstToMergeableList()
1975 AddrList.emplace_back(CI); in addInstToMergeableList()
1981 MergeableInsts.emplace_back(1, CI); in addInstToMergeableList()
2016 CombineInfo CI; in collectMergeableInsts() local
2017 CI.setMI(MI, *TII, *STM); in collectMergeableInsts()
2018 CI.Order = Order++; in collectMergeableInsts()
2020 if (!CI.hasMergeableAddress(*MRI)) in collectMergeableInsts()
2025 addInstToMergeableList(CI, MergeableInsts); in collectMergeableInsts()
2110 CombineInfo &CI = *First; in optimizeInstsWithSameBaseAddr() local
2114 if (!checkAndPrepareMerge(CI, Paired, InstsToMove)) { in optimizeInstsWithSameBaseAddr()
2121 LLVM_DEBUG(dbgs() << "Merging: " << *CI.I << " with: " << *Paired.I); in optimizeInstsWithSameBaseAddr()
2123 switch (CI.InstClass) { in optimizeInstsWithSameBaseAddr()
2129 mergeRead2Pair(CI, Paired, InstsToMove); in optimizeInstsWithSameBaseAddr()
2130 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2135 mergeWrite2Pair(CI, Paired, InstsToMove); in optimizeInstsWithSameBaseAddr()
2136 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2141 mergeSBufferLoadImmPair(CI, Paired, InstsToMove); in optimizeInstsWithSameBaseAddr()
2142 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2143 OptimizeListAgain |= (CI.Width + Paired.Width) < 16; in optimizeInstsWithSameBaseAddr()
2148 mergeBufferLoadPair(CI, Paired, InstsToMove); in optimizeInstsWithSameBaseAddr()
2149 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2150 OptimizeListAgain |= (CI.Width + Paired.Width) < 4; in optimizeInstsWithSameBaseAddr()
2155 mergeBufferStorePair(CI, Paired, InstsToMove); in optimizeInstsWithSameBaseAddr()
2156 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2157 OptimizeListAgain |= (CI.Width + Paired.Width) < 4; in optimizeInstsWithSameBaseAddr()
2162 mergeImagePair(CI, Paired, InstsToMove); in optimizeInstsWithSameBaseAddr()
2163 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2164 OptimizeListAgain |= (CI.Width + Paired.Width) < 4; in optimizeInstsWithSameBaseAddr()
2169 mergeTBufferLoadPair(CI, Paired, InstsToMove); in optimizeInstsWithSameBaseAddr()
2170 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2171 OptimizeListAgain |= (CI.Width + Paired.Width) < 4; in optimizeInstsWithSameBaseAddr()
2176 mergeTBufferStorePair(CI, Paired, InstsToMove); in optimizeInstsWithSameBaseAddr()
2177 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2178 OptimizeListAgain |= (CI.Width + Paired.Width) < 4; in optimizeInstsWithSameBaseAddr()
2182 CI.Order = Paired.Order; in optimizeInstsWithSameBaseAddr()