Lines Matching refs:AMDGPU
288 return AMDGPU::getMUBUFElements(Opc); in getOpcodeWidth()
292 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); in getOpcodeWidth()
296 return AMDGPU::getMTBUFElements(Opc); in getOpcodeWidth()
300 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getOpcodeWidth()
302 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getOpcodeWidth()
304 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getOpcodeWidth()
306 case AMDGPU::DS_READ_B32: LLVM_FALLTHROUGH; in getOpcodeWidth()
307 case AMDGPU::DS_READ_B32_gfx9: LLVM_FALLTHROUGH; in getOpcodeWidth()
308 case AMDGPU::DS_WRITE_B32: LLVM_FALLTHROUGH; in getOpcodeWidth()
309 case AMDGPU::DS_WRITE_B32_gfx9: in getOpcodeWidth()
311 case AMDGPU::DS_READ_B64: LLVM_FALLTHROUGH; in getOpcodeWidth()
312 case AMDGPU::DS_READ_B64_gfx9: LLVM_FALLTHROUGH; in getOpcodeWidth()
313 case AMDGPU::DS_WRITE_B64: LLVM_FALLTHROUGH; in getOpcodeWidth()
314 case AMDGPU::DS_WRITE_B64_gfx9: in getOpcodeWidth()
326 switch (AMDGPU::getMUBUFBaseOpcode(Opc)) { in getInstClass()
329 case AMDGPU::BUFFER_LOAD_DWORD_OFFEN: in getInstClass()
330 case AMDGPU::BUFFER_LOAD_DWORD_OFFEN_exact: in getInstClass()
331 case AMDGPU::BUFFER_LOAD_DWORD_OFFSET: in getInstClass()
332 case AMDGPU::BUFFER_LOAD_DWORD_OFFSET_exact: in getInstClass()
334 case AMDGPU::BUFFER_STORE_DWORD_OFFEN: in getInstClass()
335 case AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact: in getInstClass()
336 case AMDGPU::BUFFER_STORE_DWORD_OFFSET: in getInstClass()
337 case AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact: in getInstClass()
343 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr) == -1 && in getInstClass()
344 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0) == -1) in getInstClass()
353 switch (AMDGPU::getMTBUFBaseOpcode(Opc)) { in getInstClass()
356 case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN: in getInstClass()
357 case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN_exact: in getInstClass()
358 case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET: in getInstClass()
359 case AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET_exact: in getInstClass()
361 case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN: in getInstClass()
362 case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_exact: in getInstClass()
363 case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET: in getInstClass()
364 case AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_exact: in getInstClass()
369 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getInstClass()
370 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getInstClass()
371 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getInstClass()
373 case AMDGPU::DS_READ_B32: in getInstClass()
374 case AMDGPU::DS_READ_B32_gfx9: in getInstClass()
375 case AMDGPU::DS_READ_B64: in getInstClass()
376 case AMDGPU::DS_READ_B64_gfx9: in getInstClass()
378 case AMDGPU::DS_WRITE_B32: in getInstClass()
379 case AMDGPU::DS_WRITE_B32_gfx9: in getInstClass()
380 case AMDGPU::DS_WRITE_B64: in getInstClass()
381 case AMDGPU::DS_WRITE_B64_gfx9: in getInstClass()
383 case AMDGPU::IMAGE_BVH_INTERSECT_RAY_sa: in getInstClass()
384 case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_sa: in getInstClass()
385 case AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_sa: in getInstClass()
386 case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_sa: in getInstClass()
387 case AMDGPU::IMAGE_BVH_INTERSECT_RAY_nsa: in getInstClass()
388 case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_nsa: in getInstClass()
389 case AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa: in getInstClass()
390 case AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa: in getInstClass()
401 return AMDGPU::getMUBUFBaseOpcode(Opc); in getInstSubclass()
403 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in getInstSubclass()
408 return AMDGPU::getMTBUFBaseOpcode(Opc); in getInstSubclass()
410 case AMDGPU::DS_READ_B32: in getInstSubclass()
411 case AMDGPU::DS_READ_B32_gfx9: in getInstSubclass()
412 case AMDGPU::DS_READ_B64: in getInstSubclass()
413 case AMDGPU::DS_READ_B64_gfx9: in getInstSubclass()
414 case AMDGPU::DS_WRITE_B32: in getInstSubclass()
415 case AMDGPU::DS_WRITE_B32_gfx9: in getInstSubclass()
416 case AMDGPU::DS_WRITE_B64: in getInstSubclass()
417 case AMDGPU::DS_WRITE_B64_gfx9: in getInstSubclass()
419 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getInstSubclass()
420 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getInstSubclass()
421 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getInstSubclass()
422 return AMDGPU::S_BUFFER_LOAD_DWORD_IMM; in getInstSubclass()
430 if (AMDGPU::getMUBUFHasVAddr(Opc)) in getRegs()
432 if (AMDGPU::getMUBUFHasSrsrc(Opc)) in getRegs()
434 if (AMDGPU::getMUBUFHasSoffset(Opc)) in getRegs()
441 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in getRegs()
443 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc); in getRegs()
449 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in getRegs()
450 if (Info && AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode)->Sampler) in getRegs()
456 if (AMDGPU::getMTBUFHasVAddr(Opc)) in getRegs()
458 if (AMDGPU::getMTBUFHasSrsrc(Opc)) in getRegs()
460 if (AMDGPU::getMTBUFHasSoffset(Opc)) in getRegs()
469 case AMDGPU::S_BUFFER_LOAD_DWORD_IMM: in getRegs()
470 case AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM: in getRegs()
471 case AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM: in getRegs()
474 case AMDGPU::DS_READ_B32: in getRegs()
475 case AMDGPU::DS_READ_B64: in getRegs()
476 case AMDGPU::DS_READ_B32_gfx9: in getRegs()
477 case AMDGPU::DS_READ_B64_gfx9: in getRegs()
478 case AMDGPU::DS_WRITE_B32: in getRegs()
479 case AMDGPU::DS_WRITE_B64: in getRegs()
480 case AMDGPU::DS_WRITE_B32_gfx9: in getRegs()
481 case AMDGPU::DS_WRITE_B64_gfx9: in getRegs()
500 (Opc == AMDGPU::DS_READ_B64 || Opc == AMDGPU::DS_READ_B64_gfx9) ? 8 in setMI()
505 (Opc == AMDGPU::DS_WRITE_B64 || Opc == AMDGPU::DS_WRITE_B64_gfx9) ? 8 in setMI()
509 EltSize = AMDGPU::convertSMRDOffsetUnits(STM, 4); in setMI()
517 DMask = TII.getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
521 int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset); in setMI()
526 Format = TII.getNamedOperand(*I, AMDGPU::OpName::format)->getImm(); in setMI()
533 CPol = TII.getNamedOperand(*I, AMDGPU::OpName::cpol)->getImm(); in setMI()
541 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0) + J; in setMI()
544 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::addr); in setMI()
547 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sbase); in setMI()
550 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc); in setMI()
553 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset); in setMI()
556 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr); in setMI()
559 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::ssamp); in setMI()
676 const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe); in dmasksCanBeCombined()
677 const auto *LWEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::lwe); in dmasksCanBeCombined()
683 unsigned OperandsToMatch[] = {AMDGPU::OpName::cpol, AMDGPU::OpName::d16, in dmasksCanBeCombined()
684 AMDGPU::OpName::unorm, AMDGPU::OpName::da, in dmasksCanBeCombined()
685 AMDGPU::OpName::r128, AMDGPU::OpName::a16}; in dmasksCanBeCombined()
688 int Idx = AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), op); in dmasksCanBeCombined()
689 if (AMDGPU::getNamedOperandIdx(Paired.I->getOpcode(), op) != Idx) in dmasksCanBeCombined()
713 const llvm::AMDGPU::GcnBufferFormatInfo *OldFormatInfo = in getBufferFormatWithCompCount()
714 llvm::AMDGPU::getGcnBufferFormatInfo(OldFormat, STI); in getBufferFormatWithCompCount()
718 const llvm::AMDGPU::GcnBufferFormatInfo *NewFormatInfo = in getBufferFormatWithCompCount()
719 llvm::AMDGPU::getGcnBufferFormatInfo(OldFormatInfo->BitsPerComp, in getBufferFormatWithCompCount()
759 const llvm::AMDGPU::GcnBufferFormatInfo *Info0 = in offsetsCanBeCombined()
760 llvm::AMDGPU::getGcnBufferFormatInfo(CI.Format, STI); in offsetsCanBeCombined()
763 const llvm::AMDGPU::GcnBufferFormatInfo *Info1 = in offsetsCanBeCombined()
764 llvm::AMDGPU::getGcnBufferFormatInfo(Paired.Format, STI); in offsetsCanBeCombined()
873 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) { in getDataRegClass()
876 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::vdata)) { in getDataRegClass()
879 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0)) { in getDataRegClass()
882 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in getDataRegClass()
885 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::sdata)) { in getDataRegClass()
915 AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AMDGPU::OpName::swz); in checkAndPrepareMerge()
979 AMDGPU::getNamedOperandIdx(MBBI->getOpcode(), AMDGPU::OpName::swz); in checkAndPrepareMerge()
1035 return (EltSize == 4) ? AMDGPU::DS_READ2_B32 : AMDGPU::DS_READ2_B64; in read2Opcode()
1036 return (EltSize == 4) ? AMDGPU::DS_READ2_B32_gfx9 : AMDGPU::DS_READ2_B64_gfx9; in read2Opcode()
1041 return (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32 : AMDGPU::DS_READ2ST64_B64; in read2ST64Opcode()
1043 return (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32_gfx9 in read2ST64Opcode()
1044 : AMDGPU::DS_READ2ST64_B64_gfx9; in read2ST64Opcode()
1054 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeRead2Pair()
1056 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdst); in mergeRead2Pair()
1057 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdst); in mergeRead2Pair()
1064 unsigned SubRegIdx0 = (CI.EltSize == 4) ? AMDGPU::sub0 : AMDGPU::sub0_sub1; in mergeRead2Pair()
1065 unsigned SubRegIdx1 = (CI.EltSize == 4) ? AMDGPU::sub1 : AMDGPU::sub2_sub3; in mergeRead2Pair()
1087 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in mergeRead2Pair()
1088 BuildMI(*MBB, Paired.I, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeRead2Pair()
1091 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in mergeRead2Pair()
1132 return (EltSize == 4) ? AMDGPU::DS_WRITE2_B32 : AMDGPU::DS_WRITE2_B64; in write2Opcode()
1133 return (EltSize == 4) ? AMDGPU::DS_WRITE2_B32_gfx9 in write2Opcode()
1134 : AMDGPU::DS_WRITE2_B64_gfx9; in write2Opcode()
1139 return (EltSize == 4) ? AMDGPU::DS_WRITE2ST64_B32 in write2ST64Opcode()
1140 : AMDGPU::DS_WRITE2ST64_B64; in write2ST64Opcode()
1142 return (EltSize == 4) ? AMDGPU::DS_WRITE2ST64_B32_gfx9 in write2ST64Opcode()
1143 : AMDGPU::DS_WRITE2ST64_B64_gfx9; in write2ST64Opcode()
1154 TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeWrite2Pair()
1156 TII->getNamedOperand(*CI.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
1158 TII->getNamedOperand(*Paired.I, AMDGPU::OpName::data0); in mergeWrite2Pair()
1181 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in mergeWrite2Pair()
1182 BuildMI(*MBB, Paired.I, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg) in mergeWrite2Pair()
1185 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in mergeWrite2Pair()
1226 AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AMDGPU::OpName::dmask); in mergeImagePair()
1251 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeImagePair()
1252 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeImagePair()
1290 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::sbase)) in mergeSBufferLoadImmPair()
1301 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::sdst); in mergeSBufferLoadImmPair()
1302 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::sdst); in mergeSBufferLoadImmPair()
1337 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeBufferLoadPair()
1348 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferLoadPair()
1349 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferLoadPair()
1362 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferLoadPair()
1363 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeBufferLoadPair()
1398 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeTBufferLoadPair()
1412 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeTBufferLoadPair()
1413 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeTBufferLoadPair()
1428 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeTBufferLoadPair()
1429 const auto *Dest1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeTBufferLoadPair()
1461 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeTBufferStorePair()
1462 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeTBufferStorePair()
1464 BuildMI(*MBB, Paired.I, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg) in mergeTBufferStorePair()
1476 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeTBufferStorePair()
1490 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeTBufferStorePair()
1491 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeTBufferStorePair()
1515 return AMDGPU::getMUBUFOpcode(AMDGPU::getMUBUFBaseOpcode(CI.I->getOpcode()), in getNewOpcode()
1519 return AMDGPU::getMTBUFOpcode(AMDGPU::getMTBUFBaseOpcode(CI.I->getOpcode()), in getNewOpcode()
1529 return AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM; in getNewOpcode()
1531 return AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM; in getNewOpcode()
1535 return AMDGPU::getMaskedMIMGOp(CI.I->getOpcode(), Width); in getNewOpcode()
1554 {AMDGPU::sub0, AMDGPU::sub0_sub1, AMDGPU::sub0_sub1_sub2, AMDGPU::sub0_sub1_sub2_sub3}, in getSubRegIdxs()
1555 {AMDGPU::sub1, AMDGPU::sub1_sub2, AMDGPU::sub1_sub2_sub3, 0}, in getSubRegIdxs()
1556 {AMDGPU::sub2, AMDGPU::sub2_sub3, 0, 0}, in getSubRegIdxs()
1557 {AMDGPU::sub3, 0, 0, 0}, in getSubRegIdxs()
1584 return &AMDGPU::SReg_64_XEXECRegClass; in getTargetRegisterClass()
1586 return &AMDGPU::SGPR_128RegClass; in getTargetRegisterClass()
1588 return &AMDGPU::SGPR_256RegClass; in getTargetRegisterClass()
1590 return &AMDGPU::SGPR_512RegClass; in getTargetRegisterClass()
1616 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata); in mergeBufferStorePair()
1617 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata); in mergeBufferStorePair()
1619 BuildMI(*MBB, Paired.I, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg) in mergeBufferStorePair()
1631 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::vaddr)); in mergeBufferStorePair()
1643 MIB.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::srsrc)) in mergeBufferStorePair()
1644 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferStorePair()
1664 Register Reg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in createRegOrImm()
1667 TII->get(AMDGPU::S_MOV_B32), Reg) in createRegOrImm()
1694 const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in computeBase()
1698 Register DestSub0 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in computeBase()
1699 Register DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in computeBase()
1701 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADD_CO_U32_e64), DestSub0) in computeBase()
1710 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1) in computeBase()
1723 .addImm(AMDGPU::sub0) in computeBase()
1725 .addImm(AMDGPU::sub1); in computeBase()
1736 auto Base = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in updateBaseAndOffset()
1739 TII->getNamedOperand(MI, AMDGPU::OpName::offset)->setImm(NewOffset); in updateBaseAndOffset()
1751 if (!Def || Def->getOpcode() != AMDGPU::S_MOV_B32 || in extractConstOffset()
1774 if (!Def || Def->getOpcode() != AMDGPU::REG_SEQUENCE in processBaseWithConstOffset()
1786 if (!BaseLoDef || BaseLoDef->getOpcode() != AMDGPU::V_ADD_CO_U32_e64 || in processBaseWithConstOffset()
1787 !BaseHiDef || BaseHiDef->getOpcode() != AMDGPU::V_ADDC_U32_e64) in processBaseWithConstOffset()
1790 const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0); in processBaseWithConstOffset()
1791 const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1); in processBaseWithConstOffset()
1802 Src0 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src0); in processBaseWithConstOffset()
1803 Src1 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src1); in processBaseWithConstOffset()
1830 if (AMDGPU::getGlobalSaddrOp(MI.getOpcode()) < 0) in promoteConstantOffsetToImm()
1833 if (MI.mayLoad() && TII->getNamedOperand(MI, AMDGPU::OpName::vdata) != NULL) in promoteConstantOffsetToImm()
1841 if (TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm()) { in promoteConstantOffsetToImm()
1847 MachineOperand &Base = *TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in promoteConstantOffsetToImm()
1906 TII->getNamedOperand(MINext, AMDGPU::OpName::offset)->getImm()) in promoteConstantOffsetToImm()
1910 *TII->getNamedOperand(MINext, AMDGPU::OpName::vaddr); in promoteConstantOffsetToImm()