Lines Matching refs:getOpRegClass
296 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; in getMemOperandsWithOffsetWidth()
300 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8; in getMemOperandsWithOffsetWidth()
1843 const TargetRegisterClass *EltRC = getOpRegClass(MI, 2); in expandPostRAPseudo()
4005 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx); in verifyInstruction()
4285 const TargetRegisterClass *RC = getOpRegClass(MI, VAddr0Idx); in verifyInstruction()
4553 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI, in getOpRegClass() function in SIInstrInfo
5481 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands()
5484 if (getOpRegClass(MI, 0) == &AMDGPU::VReg_1RegClass) { in legalizeOperands()
5487 VRC = RI.hasAGPRs(getOpRegClass(MI, 0)) in legalizeOperands()
5491 VRC = RI.hasAGPRs(getOpRegClass(MI, 0)) in legalizeOperands()
5521 const TargetRegisterClass *DstRC = getOpRegClass(MI, 0); in legalizeOperands()
6750 if (!RI.hasVectorRegisters(getOpRegClass(UseMI, OpNo))) { in addUsersToMoveToVALUWorklist()
6912 const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0); in getDestEquivalentVGPRClass()
6926 const TargetRegisterClass *SrcRC = getOpRegClass(Inst, 1); in getDestEquivalentVGPRClass()