65 SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)  in SIInstrInfo()  function in SIInstrInfo
109 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,  in isReallyTriviallyReMaterializable()
127 bool SIInstrInfo::isIgnorableUse(const MachineOperand &MO) const {  in isIgnorableUse()
133 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,  in areLoadsFromSameBasePtr()
248 bool SIInstrInfo::getMemOperandsWithOffsetWidth(  in getMemOperandsWithOffsetWidth()
431 bool SIInstrInfo::shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,  in shouldClusterMemOps()
474 bool SIInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1,  in shouldScheduleLoadsNear()
486 static void reportIllegalCopy(const SIInstrInfo *TII, MachineBasicBlock &MBB,  in reportIllegalCopy()
502 static void indirectCopyToAGPR(const SIInstrInfo &TII,  in indirectCopyToAGPR()
606 static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,  in expandSGPRCopy()
654 void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,  in copyPhysReg()
969 int SIInstrInfo::commuteOpcode(unsigned Opcode) const {  in commuteOpcode()
987 void SIInstrInfo::materializeImmediate(MachineBasicBlock &MBB,  in materializeImmediate()
1044 SIInstrInfo::getPreferredSelectRegClass(unsigned Size) const {  in getPreferredSelectRegClass()
1048 void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,  in insertVectorSelect()
1073     case SIInstrInfo::SCC_TRUE: {  in insertVectorSelect()
1087     case SIInstrInfo::SCC_FALSE: {  in insertVectorSelect()
1101     case SIInstrInfo::VCCNZ: {  in insertVectorSelect()
1115     case SIInstrInfo::VCCZ: {  in insertVectorSelect()
1129     case SIInstrInfo::EXECNZ: {  in insertVectorSelect()
1147     case SIInstrInfo::EXECZ: {  in insertVectorSelect()
1174 Register SIInstrInfo::insertEQ(MachineBasicBlock *MBB,  in insertEQ()
1187 Register SIInstrInfo::insertNE(MachineBasicBlock *MBB,  in insertNE()
1200 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {  in getMovOpcode()
1215 SIInstrInfo::getIndirectGPRIDXPseudo(unsigned VecSize,  in getIndirectGPRIDXPseudo()
1316 SIInstrInfo::getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize,  in getIndirectRegWriteMovRelPseudo()
1414 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,  in storeRegToStackSlot()
1553 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,  in loadRegFromStackSlot()
1604 void SIInstrInfo::insertNoop(MachineBasicBlock &MBB,  in insertNoop()
1609 void SIInstrInfo::insertNoops(MachineBasicBlock &MBB,  in insertNoops()
1620 void SIInstrInfo::insertReturn(MachineBasicBlock &MBB) const {  in insertReturn()
1638 unsigned SIInstrInfo::getNumWaitStates(const MachineInstr &MI) {  in getNumWaitStates()
1647 bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {  in expandPostRAPseudo()
2003 SIInstrInfo::expandMovDPP64(MachineInstr &MI) const {  in expandMovDPP64()
2059 bool SIInstrInfo::swapSourceModifiers(MachineInstr &MI,  in swapSourceModifiers()
2109 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,  in commuteInstructionImpl()
2161 bool SIInstrInfo::findCommutedOpIndices(const MachineInstr &MI,  in findCommutedOpIndices()
2167 bool SIInstrInfo::findCommutedOpIndices(MCInstrDesc Desc, unsigned &SrcOpIdx0,  in findCommutedOpIndices()
2184 bool SIInstrInfo::isBranchOffsetInRange(unsigned BranchOp,  in isBranchOffsetInRange()
2200 MachineBasicBlock *SIInstrInfo::getBranchDestBlock(  in getBranchDestBlock()
2211 unsigned SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,  in insertIndirectBranch()
2320 unsigned SIInstrInfo::getBranchOpcode(SIInstrInfo::BranchPredicate Cond) {  in getBranchOpcode()
2322   case SIInstrInfo::SCC_TRUE:  in getBranchOpcode()
2324   case SIInstrInfo::SCC_FALSE:  in getBranchOpcode()
2326   case SIInstrInfo::VCCNZ:  in getBranchOpcode()
2328   case SIInstrInfo::VCCZ:  in getBranchOpcode()
2330   case SIInstrInfo::EXECNZ:  in getBranchOpcode()
2332   case SIInstrInfo::EXECZ:  in getBranchOpcode()
2339 SIInstrInfo::BranchPredicate SIInstrInfo::getBranchPredicate(unsigned Opcode) {  in getBranchPredicate()
2358 bool SIInstrInfo::analyzeBranchImpl(MachineBasicBlock &MBB,  in analyzeBranchImpl()
2401 bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,  in analyzeBranch()
2444 unsigned SIInstrInfo::removeBranch(MachineBasicBlock &MBB,  in removeBranch()
2471 unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB,  in insertBranch()
2531 bool SIInstrInfo::reverseBranchCondition(  in reverseBranchCondition()
2545 bool SIInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,  in canInsertSelect()
2587 void SIInstrInfo::insertSelect(MachineBasicBlock &MBB,  in insertSelect()
2694 bool SIInstrInfo::isFoldableCopy(const MachineInstr &MI) const {  in isFoldableCopy()
2718 unsigned SIInstrInfo::getAddressSpaceForPseudoSourceKind(  in getAddressSpaceForPseudoSourceKind()
2749 bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,  in FoldImmediate()
2998 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,  in checkInstOffsetsDoNotOverlap()
3022 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,  in areMemAccessesTriviallyDisjoint()
3096 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,  in convertToThreeAddress()
3232 bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI,  in isSchedulingBoundary()
3259 bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const {  in isAlwaysGDS()
3269 bool SIInstrInfo::modifiesModeRegister(const MachineInstr &MI) {  in modifiesModeRegister()
3283 bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const {  in hasUnwantedEffectsWhenEXECEmpty()
3324 bool SIInstrInfo::mayReadEXEC(const MachineRegisterInfo &MRI,  in mayReadEXEC()
3349 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {  in isInlineConstant()
3369 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,  in isInlineConstant()
3448 bool SIInstrInfo::isLiteralConstantLike(const MachineOperand &MO,  in isLiteralConstantLike()
3481 bool SIInstrInfo::isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,  in isImmOperandLegal()
3511 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {  in hasVALU32BitEncoding()
3523 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {  in hasModifiers()
3531 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,  in hasModifiersSet()
3537 bool SIInstrInfo::hasAnyModifiersSet(const MachineInstr &MI) const {  in hasAnyModifiersSet()
3545 bool SIInstrInfo::canShrink(const MachineInstr &MI,  in canShrink()
3618 MachineInstr *SIInstrInfo::buildShrunkInst(MachineInstr &MI,  in buildShrunkInst()
3663 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,  in usesConstantBus()
3719   if (SIInstrInfo::isVALU(MI)) {  in shouldReadExec()
3730       SIInstrInfo::isGenericOpcode(MI.getOpcode()) ||  in shouldReadExec()
3731       SIInstrInfo::isSALU(MI) ||  in shouldReadExec()
3732       SIInstrInfo::isSMRD(MI))  in shouldReadExec()
3748 bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,  in verifyInstruction()
3751   if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))  in verifyInstruction()
4419 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {  in getVALUOp()
4521 const TargetRegisterClass *SIInstrInfo::getRegClass(const MCInstrDesc &TID,  in getRegClass()
4553 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,  in getOpRegClass()
4571 void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {  in legalizeOpWithMove()
4598 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,  in buildExtractSubReg()
4630 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(  in buildExtractSubRegOrImm()
4652 void SIInstrInfo::swapOperands(MachineInstr &Inst) const {  in swapOperands()
4659 bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,  in isLegalRegOperand()
4686 bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI,  in isLegalVSrcOperand()
4697 bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,  in isOperandLegal()
4792 void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,  in legalizeOperandsVOP2()
4904 void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,  in legalizeOperandsVOP3()
4991 Register SIInstrInfo::readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI,  in readlaneVGPRToSGPR()
5033 void SIInstrInfo::legalizeOperandsSMRD(MachineRegisterInfo &MRI,  in legalizeOperandsSMRD()
5052 bool SIInstrInfo::moveFlatAddrToVGPR(MachineInstr &Inst) const {  in moveFlatAddrToVGPR()
5133 void SIInstrInfo::legalizeOperandsFLAT(MachineRegisterInfo &MRI,  in legalizeOperandsFLAT()
5151 void SIInstrInfo::legalizeGenericOperand(MachineBasicBlock &InsertMBB,  in legalizeGenericOperand()
5198 emitLoadSRsrcFromVGPRLoop(const SIInstrInfo &TII, MachineRegisterInfo &MRI,  in emitLoadSRsrcFromVGPRLoop()
5307 loadSRsrcFromVGPR(const SIInstrInfo &TII, MachineInstr &MI,  in loadSRsrcFromVGPR()
5389 extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) {  in extractRsrcPtr()
5431 SIInstrInfo::legalizeOperands(MachineInstr &MI,  in legalizeOperands()
5757 MachineBasicBlock *SIInstrInfo::moveToVALU(MachineInstr &TopInst,  in moveToVALU()
6135 SIInstrInfo::moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,  in moveScalarAddSub()
6170 void SIInstrInfo::lowerSelect(SetVectorType &Worklist, MachineInstr &Inst,  in lowerSelect()
6242 void SIInstrInfo::lowerScalarAbs(SetVectorType &Worklist,  in lowerScalarAbs()
6269 void SIInstrInfo::lowerScalarXnor(SetVectorType &Worklist,  in lowerScalarXnor()
6334 void SIInstrInfo::splitScalarNotBinop(SetVectorType &Worklist,  in splitScalarNotBinop()
6363 void SIInstrInfo::splitScalarBinOpN2(SetVectorType& Worklist,  in splitScalarBinOpN2()
6392 void SIInstrInfo::splitScalar64BitUnaryOp(  in splitScalar64BitUnaryOp()
6449 void SIInstrInfo::splitScalar64BitAddSub(SetVectorType &Worklist,  in splitScalar64BitAddSub()
6521 void SIInstrInfo::splitScalar64BitBinaryOp(SetVectorType &Worklist,  in splitScalar64BitBinaryOp()
6585 void SIInstrInfo::splitScalar64BitXnor(SetVectorType &Worklist,  in splitScalar64BitXnor()
6627 void SIInstrInfo::splitScalar64BitBCNT(  in splitScalar64BitBCNT()
6664 void SIInstrInfo::splitScalar64BitBFE(SetVectorType &Worklist,  in splitScalar64BitBFE()
6725 void SIInstrInfo::addUsersToMoveToVALUWorklist(  in addUsersToMoveToVALUWorklist()
6762 void SIInstrInfo::movePackToVALU(SetVectorType &Worklist,  in movePackToVALU()
6824 void SIInstrInfo::addSCCDefUsersToVALUWorklist(MachineOperand &Op,  in addSCCDefUsersToVALUWorklist()
6889 void SIInstrInfo::addSCCDefsToVALUWorklist(MachineOperand &Op,  in addSCCDefsToVALUWorklist()
6910 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(  in getDestEquivalentVGPRClass()
6960 Register SIInstrInfo::findUsedSGPR(const MachineInstr &MI,  in findUsedSGPR()
7029 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,  in getNamedOperand()
7038 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {  in getDefaultRsrcDataFormat()
7060 uint64_t SIInstrInfo::getScratchRsrcWords23() const {  in getScratchRsrcWords23()
7084 bool SIInstrInfo::isLowLatencyInstruction(const MachineInstr &MI) const {  in isLowLatencyInstruction()
7090 bool SIInstrInfo::isHighLatencyDef(int Opc) const {  in isHighLatencyDef()
7095 unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,  in isStackAccess()
7108 unsigned SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI,  in isSGPRStackAccess()
7116 unsigned SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,  in isLoadFromStackSlot()
7130 unsigned SIInstrInfo::isStoreToStackSlot(const MachineInstr &MI,  in isStoreToStackSlot()
7144 unsigned SIInstrInfo::getInstBundleSize(const MachineInstr &MI) const {  in getInstBundleSize()
7156 unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {  in getInstSizeInBytes()
7227 bool SIInstrInfo::mayAccessFlatAddressSpace(const MachineInstr &MI) const {  in mayAccessFlatAddressSpace()
7241 bool SIInstrInfo::isNonUniformBranchInstr(MachineInstr &Branch) const {  in isNonUniformBranchInstr()
7245 void SIInstrInfo::convertNonUniformIfRegion(MachineBasicBlock *IfEntry,  in convertNonUniformIfRegion()
7270 void SIInstrInfo::convertNonUniformLoopRegion(  in convertNonUniformLoopRegion()
7318 SIInstrInfo::getSerializableTargetIndices() const {  in getSerializableTargetIndices()
7331 SIInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,  in CreateTargetPostRAHazardRecognizer()
7339 SIInstrInfo::CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {  in CreateTargetPostRAHazardRecognizer()
7344 SIInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {  in decomposeMachineOperandsTargetFlags()
7349 SIInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {  in getSerializableDirectMachineOperandTargetFlags()
7363 bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI) const {  in isBasicBlockPrologue()
7369 SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB,  in getAddNoCarry()
7384 MachineInstrBuilder SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB,  in getAddNoCarry()
7405 bool SIInstrInfo::isKillTerminator(unsigned Opcode) {  in isKillTerminator()
7415 const MCInstrDesc &SIInstrInfo::getKillTerminatorFromPseudo(unsigned Opcode) const {  in getKillTerminatorFromPseudo()
7426 void SIInstrInfo::fixImplicitOperands(MachineInstr &MI) const {  in fixImplicitOperands()
7436 bool SIInstrInfo::isBufferSMRD(const MachineInstr &MI) const {  in isBufferSMRD()
7479 bool SIInstrInfo::isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,  in isLegalFLATOffset()
7506 SIInstrInfo::splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace,  in splitFlatOffset()
7568 bool SIInstrInfo::isAsmOnlyOpcode(int MCOp) const {  in isAsmOnlyOpcode()
7588 int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {  in pseudoToMCOpcode()
7810 MachineInstr *SIInstrInfo::createPHIDestinationCopy(  in createPHIDestinationCopy()
7825 MachineInstr *SIInstrInfo::createPHISourceCopy(  in createPHISourceCopy()
7845 bool llvm::SIInstrInfo::isWave32() const { return ST.isWave32(); }  in isWave32()
7847 MachineInstr *SIInstrInfo::foldMemoryOperandImpl(  in foldMemoryOperandImpl()
7884 unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()
7901 unsigned SIInstrInfo::getDSShaderTypeValue(const MachineFunction &MF) {  in getDSShaderTypeValue()