Lines Matching refs:Rsrc
5200 const DebugLoc &DL, MachineOperand &Rsrc) { in emitLoadSRsrcFromVGPRLoop() argument
5218 Register VRsrc = Rsrc.getReg(); in emitLoadSRsrcFromVGPRLoop()
5219 unsigned VRsrcUndef = getUndefRegState(Rsrc.isUndef()); in emitLoadSRsrcFromVGPRLoop()
5221 unsigned RegSize = TRI->getRegSizeInBits(Rsrc.getReg(), MRI); in emitLoadSRsrcFromVGPRLoop()
5282 Rsrc.setReg(SRsrc); in emitLoadSRsrcFromVGPRLoop()
5283 Rsrc.setIsKill(true); in emitLoadSRsrcFromVGPRLoop()
5308 MachineOperand &Rsrc, MachineDominatorTree *MDT, in loadSRsrcFromVGPR() argument
5379 emitLoadSRsrcFromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, Rsrc); in loadSRsrcFromVGPR()
5389 extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) { in extractRsrcPtr() argument
5396 TII.buildExtractSubReg(MI, MRI, Rsrc, &AMDGPU::VReg_128RegClass, in extractRsrcPtr()
5617 MachineOperand *Rsrc = &MI.getOperand(RsrcIdx); in legalizeOperands() local
5619 if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()), in legalizeOperands()
5654 std::tie(RsrcPtr, NewSRsrc) = extractRsrcPtr(*this, MI, *Rsrc); in legalizeOperands()
5680 Rsrc->setReg(NewSRsrc); in legalizeOperands()
5688 std::tie(RsrcPtr, NewSRsrc) = extractRsrcPtr(*this, MI, *Rsrc); in legalizeOperands()
5750 CreatedBB = loadSRsrcFromVGPR(*this, MI, *Rsrc, MDT); in legalizeOperands()