Lines Matching refs:RI
67 RI(ST), ST(ST) { in SIInstrInfo()
510 const SIRegisterInfo &RI = TII.getRegisterInfo(); in indirectCopyToAGPR() local
518 if (!Def->definesRegister(SrcReg, &RI)) in indirectCopyToAGPR()
531 if (I->modifiesRegister(DefOp.getReg(), &RI)) in indirectCopyToAGPR()
559 unsigned MaxVGPRs = RI.getRegPressureLimit(&AMDGPU::VGPR_32RegClass, in indirectCopyToAGPR()
576 if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs) in indirectCopyToAGPR()
610 const SIRegisterInfo &RI = TII.getRegisterInfo(); in expandSGPRCopy() local
611 ArrayRef<int16_t> BaseIndices = RI.getRegSplitParts(RC, 4); in expandSGPRCopy()
617 Register Reg = RI.getSubReg(DestReg, SubIdx); in expandSGPRCopy()
621 Register Src = RI.getSubReg(SrcReg, SubIdx); in expandSGPRCopy()
626 unsigned Channel = RI.getChannelFromSubReg(SubIdx); in expandSGPRCopy()
627 SubIdx = RI.getSubRegFromChannel(Channel, 2); in expandSGPRCopy()
632 LastMI = BuildMI(MBB, I, DL, TII.get(Opcode), RI.getSubReg(DestReg, SubIdx)) in expandSGPRCopy()
633 .addReg(RI.getSubReg(SrcReg, SubIdx)) in expandSGPRCopy()
651 LastMI->addRegisterKilled(SrcReg, &RI); in expandSGPRCopy()
658 const TargetRegisterClass *RC = RI.getPhysRegClass(DestReg); in copyPhysReg()
663 ((RI.getRegSizeInBits(*RC) == 16) ^ in copyPhysReg()
664 (RI.getRegSizeInBits(*RI.getPhysRegClass(SrcReg)) == 16))) { in copyPhysReg()
665 MCRegister &RegToFix = (RI.getRegSizeInBits(*RC) == 16) ? DestReg : SrcReg; in copyPhysReg()
666 MCRegister Super = RI.get32BitRegister(RegToFix); in copyPhysReg()
667 assert(RI.getSubReg(Super, AMDGPU::lo16) == RegToFix); in copyPhysReg()
676 RC = RI.getPhysRegClass(DestReg); in copyPhysReg()
798 const unsigned Size = RI.getRegSizeInBits(*RC); in copyPhysReg()
815 MCRegister NewDestReg = RI.get32BitRegister(DestReg); in copyPhysReg()
816 MCRegister NewSrcReg = RI.get32BitRegister(SrcReg); in copyPhysReg()
865 const TargetRegisterClass *SrcRC = RI.getPhysRegClass(SrcReg); in copyPhysReg()
866 if (RC == RI.getVGPR64Class() && (SrcRC == RC || RI.isSGPRClass(SrcRC))) { in copyPhysReg()
883 const bool Forward = RI.getHWRegIndex(DestReg) <= RI.getHWRegIndex(SrcReg); in copyPhysReg()
884 if (RI.isSGPRClass(RC)) { in copyPhysReg()
885 if (!RI.isSGPRClass(SrcRC)) { in copyPhysReg()
895 if (RI.hasAGPRs(RC)) { in copyPhysReg()
896 Opcode = (RI.hasVGPRs(SrcRC)) ? in copyPhysReg()
898 } else if (RI.hasVGPRs(RC) && RI.hasAGPRs(SrcRC)) { in copyPhysReg()
900 } else if ((Size % 64 == 0) && RI.hasVGPRs(RC) && in copyPhysReg()
901 (RI.isProperlyAlignedRC(*RC) && in copyPhysReg()
902 (SrcRC == RC || RI.isSGPRClass(SrcRC)))) { in copyPhysReg()
919 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RC, EltSize); in copyPhysReg()
923 const bool CanKillSuperReg = KillSrc && !RI.regsOverlap(SrcReg, DestReg); in copyPhysReg()
937 indirectCopyToAGPR(*this, MBB, MI, DL, RI.getSubReg(DestReg, SubIdx), in copyPhysReg()
938 RI.getSubReg(SrcReg, SubIdx), UseKill, *RS, in copyPhysReg()
941 Register DstSubReg = RI.getSubReg(DestReg, SubIdx); in copyPhysReg()
942 Register SrcSubReg = RI.getSubReg(SrcReg, SubIdx); in copyPhysReg()
959 BuildMI(MBB, MI, DL, get(Opcode), RI.getSubReg(DestReg, SubIdx)) in copyPhysReg()
960 .addReg(RI.getSubReg(SrcReg, SubIdx)); in copyPhysReg()
1023 if (RI.isSGPRClass(RegClass)) { in materializeImmediate()
1024 if (RI.getRegSizeInBits(*RegClass) > 32) { in materializeImmediate()
1033 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RegClass, EltSize); in materializeImmediate()
1038 get(Opcode), RI.getSubReg(DestReg, SubIndices[Idx])); in materializeImmediate()
1056 RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in insertVectorSelect()
1131 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC()); in insertVectorSelect()
1149 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC()); in insertVectorSelect()
1179 Register Reg = MRI.createVirtualRegister(RI.getBoolRC()); in insertEQ()
1192 Register Reg = MRI.createVirtualRegister(RI.getBoolRC()); in insertNE()
1202 if (RI.hasAGPRs(DstRC)) in getMovOpcode()
1204 if (RI.getRegSizeInBits(*DstRC) == 32) { in getMovOpcode()
1205 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in getMovOpcode()
1206 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) { in getMovOpcode()
1208 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) { in getMovOpcode()
1432 if (RI.isSGPRClass(RC)) { in storeRegToStackSlot()
1455 if (RI.spillSGPRToVGPR()) in storeRegToStackSlot()
1460 unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillSaveOpcode(SpillSize) in storeRegToStackSlot()
1571 if (RI.isSGPRClass(RC)) { in loadRegFromStackSlot()
1585 if (RI.spillSGPRToVGPR()) in loadRegFromStackSlot()
1595 unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillRestoreOpcode(SpillSize) in loadRegFromStackSlot()
1713 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo()
1714 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo()
1745 !RI.isAGPR(MBB.getParent()->getRegInfo(), SrcOp.getReg())) { in expandPostRAPseudo()
1758 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) in expandPostRAPseudo()
1761 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) in expandPostRAPseudo()
1782 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo()
1783 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo()
1846 if (RI.hasVGPRs(EltRC)) { in expandPostRAPseudo()
1849 Opc = RI.getRegSizeInBits(*EltRC) == 64 ? AMDGPU::S_MOVRELD_B64 in expandPostRAPseudo()
1861 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
1895 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
1934 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
1948 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo()
1949 Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1); in expandPostRAPseudo()
2017 MovDPP.addDef(RI.getSubReg(Dst, Sub)); in expandMovDPP64()
2035 MovDPP.addReg(RI.getSubReg(Src, Sub)); in expandMovDPP64()
2562 return RI.hasVGPRs(RC) && NumInsts <= 6; in canInsertSelect()
2580 return RI.isSGPRClass(RC); in canInsertSelect()
2599 unsigned DstSize = RI.getRegSizeInBits(*DstRC); in insertSelect()
2778 bool isVGPRCopy = RI.isVGPR(*MRI, DstReg); in FoldImmediate()
2785 if (RI.isAGPR(*MRI, DstReg)) { in FoldImmediate()
2801 DstReg = RI.get32BitRegister(DstReg); in FoldImmediate()
2841 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))) in FoldImmediate()
2844 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg()))) in FoldImmediate()
2908 RI.isSGPRClass(RI.getPhysRegClass(Src0->getReg())))) || in FoldImmediate()
2911 RI.isSGPRClass(MRI->getRegClass(Src0->getReg()))))) in FoldImmediate()
2925 RI.isSGPRClass(RI.getPhysRegClass(Src1->getReg()))) || in FoldImmediate()
2927 RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))) in FoldImmediate()
3005 Dummy0, &RI) || in checkInstOffsetsDoNotOverlap()
3007 Dummy1, &RI)) in checkInstOffsetsDoNotOverlap()
3152 !RI.isSGPRReg(MBB->getParent()->getRegInfo(), Src0->getReg()))) { in convertToThreeAddress()
3253 return MI.modifiesRegister(AMDGPU::EXEC, &RI) || in isSchedulingBoundary()
3331 if (!RI.isSGPRReg(MRI, MI.getOperand(0).getReg())) in mayReadEXEC()
3335 return MI.readsRegister(AMDGPU::EXEC, &RI); in mayReadEXEC()
3346 return !isSALU(MI) || MI.readsRegister(AMDGPU::EXEC, &RI); in mayReadEXEC()
3499 return RI.opCanUseInlineConstant(OpInfo.OperandType); in isImmOperandLegal()
3502 if (!RI.opCanUseLiteralConstant(OpInfo.OperandType)) in isImmOperandLegal()
3564 if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg())) in canShrink()
3574 if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) || in canShrink()
3585 if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) || in canShrink()
3679 return RI.isSGPRClass(MRI.getRegClass(MO.getReg())); in usesConstantBus()
3773 const TargetRegisterClass *RC = MI.getRegClassConstraint(I, this, &RI); in verifyInstruction()
3859 const TargetRegisterClass *RC = RI.getRegClassForReg(MRI, Reg); in verifyInstruction()
3860 const bool IsVGPR = RI.hasVGPRs(RC); in verifyInstruction()
3861 const bool IsAGPR = !IsVGPR && RI.hasAGPRs(RC); in verifyInstruction()
3864 RI.getSubRegClass(RC, MO.getSubReg()); in verifyInstruction()
3865 RC = RI.getCompatibleSubRegClass(RC, SubRC, MO.getSubReg()); in verifyInstruction()
3871 if (!RC || !RI.isProperlyAlignedRC(*RC)) { in verifyInstruction()
3881 const TargetRegisterClass *RC = RI.getRegClass(RegClass); in verifyInstruction()
3907 if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) { in verifyInstruction()
4006 uint32_t DstSize = RI.getRegSizeInBits(*DstRC) / 32; in verifyInstruction()
4065 return !RI.regsOverlap(SGPRUsed, SGPR); in verifyInstruction()
4215 !isSubRegOf(RI, ImpUse, IsDst ? *Dst : Src0)) { in verifyInstruction()
4372 (RI.isAGPR(MRI, Dst->getReg()) != RI.isAGPR(MRI, Data->getReg()))) { in verifyInstruction()
4378 (RI.isAGPR(MRI, Data->getReg()) != RI.isAGPR(MRI, Data2->getReg()))) { in verifyInstruction()
4384 if ((Dst && RI.isAGPR(MRI, Dst->getReg())) || in verifyInstruction()
4385 (Data && RI.isAGPR(MRI, Data->getReg())) || in verifyInstruction()
4386 (Data2 && RI.isAGPR(MRI, Data2->getReg()))) { in verifyInstruction()
4402 Aligned = !(RI.getHWRegIndex(Reg) & 1); in verifyInstruction()
4405 Aligned = RI.getRegSizeInBits(RC) > 32 && RI.isProperlyAlignedRC(RC) && in verifyInstruction()
4406 !(RI.getChannelFromSubReg(Op->getSubReg()) & 1); in verifyInstruction()
4433 RI.isAGPR(MRI, MI.getOperand(0).getReg()) ? in getVALUOp()
4550 return RI.getRegClass(RegClass); in getRegClass()
4563 return RI.getPhysRegClass(Reg); in getOpRegClass()
4568 return RI.getRegClass(RCID); in getOpRegClass()
4577 const TargetRegisterClass *RC = RI.getRegClass(RCID); in legalizeOpWithMove()
4578 unsigned Size = RI.getRegSizeInBits(*RC); in legalizeOpWithMove()
4582 else if (RI.isSGPRClass(RC)) in legalizeOpWithMove()
4585 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC); in legalizeOpWithMove()
4586 const TargetRegisterClass *VRC64 = RI.getVGPR64Class(); in legalizeOpWithMove()
4587 if (RI.getCommonSubClass(VRC64, VRC)) in legalizeOpWithMove()
4667 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass); in isLegalRegOperand()
4675 const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF); in isLegalRegOperand()
4679 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); in isLegalRegOperand()
4704 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr; in isOperandLegal()
4747 bool IsAGPR = RI.isAGPR(MRI, MO->getReg()); in isOperandLegal()
4761 RI.isAGPR(MRI, MI.getOperand(DataIdx).getReg()) != IsAGPR) in isOperandLegal()
4765 RI.isAGPR(MRI, MI.getOperand(VDstIdx).getReg()) != IsAGPR) in isOperandLegal()
4771 RI.isAGPR(MRI, MI.getOperand(Data1Idx).getReg()) != IsAGPR) in isOperandLegal()
4776 RI.isSGPRReg(MRI, MO->getReg())) in isOperandLegal()
4807 Src0.isReg() && (RI.isSGPRReg(MRI, Src0.getReg()) || in legalizeOperandsVOP2()
4816 if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) { in legalizeOperandsVOP2()
4822 if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) { in legalizeOperandsVOP2()
4833 if (Src0.isReg() && RI.isAGPR(MRI, Src0.getReg())) in legalizeOperandsVOP2()
4836 if (Src1.isReg() && RI.isAGPR(MRI, Src1.getReg())) in legalizeOperandsVOP2()
4848 RI.isVGPR(MRI, Src1.getReg())) { in legalizeOperandsVOP2()
4920 if (Src1.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) { in legalizeOperandsVOP3()
4926 if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) { in legalizeOperandsVOP3()
4966 if (RI.hasAGPRs(MRI.getRegClass(MO.getReg())) && in legalizeOperandsVOP3()
4972 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg()))) in legalizeOperandsVOP3()
4994 const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC); in readlaneVGPRToSGPR()
4996 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32; in readlaneVGPRToSGPR()
4998 if (RI.hasAGPRs(VRC)) { in readlaneVGPRToSGPR()
4999 VRC = RI.getEquivalentVGPRClass(VRC); in readlaneVGPRToSGPR()
5019 .addReg(SrcReg, 0, RI.getSubRegFromChannel(i)); in readlaneVGPRToSGPR()
5028 MIB.addImm(RI.getSubRegFromChannel(i)); in readlaneVGPRToSGPR()
5041 if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) { in legalizeOperandsSMRD()
5046 if (SOff && !RI.isSGPRClass(MRI.getRegClass(SOff->getReg()))) { in legalizeOperandsSMRD()
5068 if (RI.isSGPRReg(MRI, SAddr.getReg())) in moveFlatAddrToVGPR()
5141 if (!SAddr || RI.isSGPRClass(MRI.getRegClass(SAddr->getReg()))) in legalizeOperandsFLAT()
5160 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand()
5161 RI.getRegClassForReg(MRI, OpReg), OpSubReg); in legalizeGenericOperand()
5189 if (!RI.isSGPRClass(DstRC) && !Copy->readsRegister(AMDGPU::EXEC, &RI) && in legalizeGenericOperand()
5471 if (RI.hasVectorRegisters(OpRC)) { in legalizeOperands()
5481 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands()
5487 VRC = RI.hasAGPRs(getOpRegClass(MI, 0)) in legalizeOperands()
5488 ? RI.getEquivalentAGPRClass(SRC) in legalizeOperands()
5489 : RI.getEquivalentVGPRClass(SRC); in legalizeOperands()
5491 VRC = RI.hasAGPRs(getOpRegClass(MI, 0)) in legalizeOperands()
5492 ? RI.getEquivalentAGPRClass(VRC) in legalizeOperands()
5493 : RI.getEquivalentVGPRClass(VRC); in legalizeOperands()
5522 if (RI.hasVGPRs(DstRC)) { in legalizeOperands()
5532 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); in legalizeOperands()
5562 if (Src.isReg() && RI.hasVectorRegisters(MRI.getRegClass(Src.getReg()))) in legalizeOperands()
5575 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) in legalizeOperands()
5579 if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg()))) in legalizeOperands()
5588 if (!RI.isSGPRClass(MRI.getRegClass(Dest->getReg()))) { in legalizeOperands()
5619 if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()), in legalizeOperands()
5620 RI.getRegClass(RsrcRC))) { in legalizeOperands()
5649 const auto *BoolXExecRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in legalizeOperands()
5959 const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in moveToVALU()
5970 Register DestReg = MRI.createVirtualRegister(RI.getEquivalentVGPRClass( in moveToVALU()
5999 RI.getEquivalentVGPRClass(MRI.getRegClass(Dest0.getReg())); in moveToVALU()
6097 NewDstRC == RI.getRegClassForReg(MRI, Inst.getOperand(1).getReg())) { in moveToVALU()
6189 if (CandI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != in lowerSelect()
6297 RI.isSGPRClass(MRI.getRegClass(Src0.getReg())); in lowerScalarXnor()
6299 RI.isSGPRClass(MRI.getRegClass(Src1.getReg())); in lowerScalarXnor()
6409 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
6415 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitUnaryOp()
6416 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
6456 const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID); in splitScalar64BitAddSub()
6473 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitAddSub()
6474 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitAddSub()
6539 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
6544 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
6556 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC); in splitScalar64BitBinaryOp()
6557 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
6605 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) { in splitScalar64BitXnor()
6646 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0); in splitScalar64BitBCNT()
6750 if (!RI.hasVectorRegisters(getOpRegClass(UseMI, OpNo))) { in addUsersToMoveToVALUWorklist()
6839 if (MI.findRegisterUseOperandIdx(AMDGPU::SCC, false, &RI) != -1) { in addSCCDefUsersToVALUWorklist()
6847 User.getOperand(4).setReg(RI.getVCC()); in addSCCDefUsersToVALUWorklist()
6850 User.getOperand(5).setReg(RI.getVCC()); in addSCCDefUsersToVALUWorklist()
6871 if (MI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != -1) in addSCCDefUsersToVALUWorklist()
6880 .addReg(RI.getVCC()); in addSCCDefUsersToVALUWorklist()
6901 if (MI.modifiesRegister(AMDGPU::VCC, &RI)) in addSCCDefsToVALUWorklist()
6903 if (MI.definesRegister(AMDGPU::SCC, &RI)) { in addSCCDefsToVALUWorklist()
6927 if (RI.hasAGPRs(SrcRC)) { in getDestEquivalentVGPRClass()
6928 if (RI.hasAGPRs(NewDstRC)) in getDestEquivalentVGPRClass()
6935 NewDstRC = RI.getEquivalentAGPRClass(NewDstRC); in getDestEquivalentVGPRClass()
6938 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC); in getDestEquivalentVGPRClass()
6944 if (RI.hasVGPRs(NewDstRC) || NewDstRC == &AMDGPU::VReg_1RegClass) in getDestEquivalentVGPRClass()
6947 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC); in getDestEquivalentVGPRClass()
6991 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass); in findUsedSGPR()
6992 bool IsRequiredSGPR = RI.isSGPRClass(OpRC); in findUsedSGPR()
6999 if (RI.isSGPRClass(RegRC)) in findUsedSGPR()
7255 Register DstReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformIfRegion()
7282 Register DstReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformLoopRegion()
7283 Register BackEdgeReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformLoopRegion()
7293 Register ZeroReg = MRI.createVirtualRegister(RI.getBoolRC()); in convertNonUniformLoopRegion()
7365 MI.modifiesRegister(AMDGPU::EXEC, &RI); in isBasicBlockPrologue()
7377 Register UnusedCarry = MRI.createVirtualRegister(RI.getBoolRC()); in getAddNoCarry()
7378 MRI.setRegAllocationHint(UnusedCarry, 0, RI.getVCC()); in getAddNoCarry()
7394 ? Register(RI.getVCC()) in getAddNoCarry()
7395 : RS.scavengeRegister(RI.getBoolRC(), I, 0, false); in getAddNoCarry()
7446 return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass); in isBufferSMRD()