5199                           MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB,  in emitLoadSRsrcFromVGPRLoop()  argument
5213   MachineBasicBlock::iterator I = LoopBB.begin();  in emitLoadSRsrcFromVGPRLoop()
5231     BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), CurRegLo)  in emitLoadSRsrcFromVGPRLoop()
5235     BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), CurRegHi)  in emitLoadSRsrcFromVGPRLoop()
5243     BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), CurReg)  in emitLoadSRsrcFromVGPRLoop()
5251         BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), NewCondReg)  in emitLoadSRsrcFromVGPRLoop()
5263       BuildMI(LoopBB, I, DL, TII.get(AndOpc), AndReg)  in emitLoadSRsrcFromVGPRLoop()
5274   auto Merge = BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc);  in emitLoadSRsrcFromVGPRLoop()
5289   BuildMI(LoopBB, I, DL, TII.get(SaveExecOpc), SaveExec)  in emitLoadSRsrcFromVGPRLoop()
5293   I = LoopBB.end();  in emitLoadSRsrcFromVGPRLoop()
5296   BuildMI(LoopBB, I, DL, TII.get(XorTermOpc), Exec)  in emitLoadSRsrcFromVGPRLoop()
5300   BuildMI(LoopBB, I, DL, TII.get(AMDGPU::SI_WATERFALL_LOOP)).addMBB(&LoopBB);  in emitLoadSRsrcFromVGPRLoop()
5346   MachineBasicBlock *LoopBB = MF.CreateMachineBasicBlock();  in loadSRsrcFromVGPR()  local
5351   MF.insert(MBBI, LoopBB);  in loadSRsrcFromVGPR()
5354   LoopBB->addSuccessor(LoopBB);  in loadSRsrcFromVGPR()
5355   LoopBB->addSuccessor(RemainderBB);  in loadSRsrcFromVGPR()
5361   LoopBB->splice(LoopBB->begin(), &MBB, Begin, MBB.end());  in loadSRsrcFromVGPR()
5363   MBB.addSuccessor(LoopBB);  in loadSRsrcFromVGPR()
5370     MDT->addNewBlock(LoopBB, &MBB);  in loadSRsrcFromVGPR()
5371     MDT->addNewBlock(RemainderBB, LoopBB);  in loadSRsrcFromVGPR()
5379   emitLoadSRsrcFromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, Rsrc);  in loadSRsrcFromVGPR()
5384   return LoopBB;  in loadSRsrcFromVGPR()