1055   const TargetRegisterClass *BoolXExecRC =  in insertVectorSelect()  local
1061     Register SReg = MRI.createVirtualRegister(BoolXExecRC);  in insertVectorSelect()
1074       Register SReg = MRI.createVirtualRegister(BoolXExecRC);  in insertVectorSelect()
1088       Register SReg = MRI.createVirtualRegister(BoolXExecRC);  in insertVectorSelect()
1104       Register SReg = MRI.createVirtualRegister(BoolXExecRC);  in insertVectorSelect()
1118       Register SReg = MRI.createVirtualRegister(BoolXExecRC);  in insertVectorSelect()
1130       Register SReg = MRI.createVirtualRegister(BoolXExecRC);  in insertVectorSelect()
1148       Register SReg = MRI.createVirtualRegister(BoolXExecRC);  in insertVectorSelect()
5211   const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in emitLoadSRsrcFromVGPRLoop()  local
5249     Register NewCondReg = MRI.createVirtualRegister(BoolXExecRC);  in emitLoadSRsrcFromVGPRLoop()
5262       Register AndReg = MRI.createVirtualRegister(BoolXExecRC);  in emitLoadSRsrcFromVGPRLoop()
5285   Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);  in emitLoadSRsrcFromVGPRLoop()
5325   const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in loadSRsrcFromVGPR()  local
5327   Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);  in loadSRsrcFromVGPR()
5649       const auto *BoolXExecRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);  in legalizeOperands()  local
5650       Register CondReg0 = MRI.createVirtualRegister(BoolXExecRC);  in legalizeOperands()
5651       Register CondReg1 = MRI.createVirtualRegister(BoolXExecRC);  in legalizeOperands()