Lines Matching refs:has16BitInsts

129   if (Subtarget->has16BitInsts()) {  in SITargetLowering()
445   if (Subtarget->has16BitInsts()) {  in SITargetLowering()
531   if (Subtarget->has16BitInsts()) {  in SITargetLowering()
785   if (Subtarget->has16BitInsts()) {  in SITargetLowering()
932       if (Subtarget->has16BitInsts())  in getRegisterTypeForCallingConv()
938       return Subtarget->has16BitInsts() ? MVT::i16 : MVT::i32;  in getRegisterTypeForCallingConv()
960     if (Size == 16 && Subtarget->has16BitInsts())  in getNumRegistersForCallingConv()
985     if (Size == 16 && Subtarget->has16BitInsts()) {  in getVectorTypeBreakdownForCallingConv()
999     if (Size < 16 && Subtarget->has16BitInsts()) {  in getVectorTypeBreakdownForCallingConv()
1624   if (Subtarget->has16BitInsts() && VT == MVT::i16) {  in isTypeDesirableForOp()
4403   return (Ty.getScalarSizeInBits() <= 16 && Subtarget->has16BitInsts())  in getPreferredShiftAmountTy()
4445     return Subtarget->has16BitInsts() && hasFP64FP16Denormals(MF);  in isFMAFasterThanFMulAndFAdd()
9389   if (!Subtarget->has16BitInsts() ||  in performZeroExtendCombine()
9986        (VT == MVT::f16 && Subtarget->has16BitInsts()) ||  in performMinMaxCombine()
10698   if (VT != MVT::f32 && VT != MVT::f64 && (Subtarget->has16BitInsts() &&  in performSetCCCombine()
11622   if (Size == 16 && !Subtarget->has16BitInsts())  in getAsmOperandConstVal()