Lines Matching refs:SL
1650 const SDLoc &SL, in lowerKernArgParameterPtr() argument
1666 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL, in lowerKernArgParameterPtr()
1669 return DAG.getObjectPtrOffset(SL, BasePtr, TypeSize::Fixed(Offset)); in lowerKernArgParameterPtr()
1673 const SDLoc &SL) const { in getImplicitArgPtr()
1676 return lowerKernArgParameterPtr(DAG, SL, DAG.getEntryNode(), Offset); in getImplicitArgPtr()
1680 const SDLoc &SL, SDValue Val, in convertArgType() argument
1689 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val, in convertArgType()
1690 DAG.getConstant(0, SL, MVT::i32)); in convertArgType()
1697 Val = DAG.getNode(Opc, SL, MemVT, Val, DAG.getValueType(VT)); in convertArgType()
1701 Val = getFPExtOrFPRound(DAG, Val, SL, VT); in convertArgType()
1703 Val = DAG.getSExtOrTrunc(Val, SL, VT); in convertArgType()
1705 Val = DAG.getZExtOrTrunc(Val, SL, VT); in convertArgType()
1711 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Chain, in lowerKernargMemParameter() argument
1728 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, AlignDownOffset); in lowerKernargMemParameter()
1729 SDValue Load = DAG.getLoad(MVT::i32, SL, Chain, Ptr, PtrInfo, Align(4), in lowerKernargMemParameter()
1733 SDValue ShiftAmt = DAG.getConstant(OffsetDiff * 8, SL, MVT::i32); in lowerKernargMemParameter()
1734 SDValue Extract = DAG.getNode(ISD::SRL, SL, MVT::i32, Load, ShiftAmt); in lowerKernargMemParameter()
1736 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract); in lowerKernargMemParameter()
1737 ArgVal = DAG.getNode(ISD::BITCAST, SL, MemVT, ArgVal); in lowerKernargMemParameter()
1738 ArgVal = convertArgType(DAG, VT, MemVT, SL, ArgVal, Signed, Arg); in lowerKernargMemParameter()
1741 return DAG.getMergeValues({ ArgVal, Load.getValue(1) }, SL); in lowerKernargMemParameter()
1744 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, Offset); in lowerKernargMemParameter()
1745 SDValue Load = DAG.getLoad(MemVT, SL, Chain, Ptr, PtrInfo, Alignment, in lowerKernargMemParameter()
1749 SDValue Val = convertArgType(DAG, VT, MemVT, SL, Load, Signed, Arg); in lowerKernargMemParameter()
1750 return DAG.getMergeValues({ Val, Load.getValue(1) }, SL); in lowerKernargMemParameter()
1754 const SDLoc &SL, SDValue Chain, in lowerStackParameter() argument
1796 ExtType, SL, VA.getLocVT(), Chain, FIN, in lowerStackParameter()
2828 SDLoc SL; in passSpecialInputs() local
2836 Y = DAG.getNode(ISD::SHL, SL, MVT::i32, Y, in passSpecialInputs()
2837 DAG.getShiftAmountConstant(10, MVT::i32, SL)); in passSpecialInputs()
2839 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Y) : Y; in passSpecialInputs()
2844 Z = DAG.getNode(ISD::SHL, SL, MVT::i32, Z, in passSpecialInputs()
2845 DAG.getShiftAmountConstant(20, MVT::i32, SL)); in passSpecialInputs()
2847 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Z) : Z; in passSpecialInputs()
4484 SDLoc SL(Op); in splitUnaryVectorOp() local
4485 SDValue OpLo = DAG.getNode(Opc, SL, Lo.getValueType(), Lo, in splitUnaryVectorOp()
4487 SDValue OpHi = DAG.getNode(Opc, SL, Hi.getValueType(), Hi, in splitUnaryVectorOp()
4507 SDLoc SL(Op); in splitBinaryVectorOp() local
4509 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1, in splitBinaryVectorOp()
4511 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, in splitBinaryVectorOp()
4531 SDLoc SL(Op); in splitTernaryVectorOp() local
4533 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1, Lo2, in splitTernaryVectorOp()
4535 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, Hi2, in splitTernaryVectorOp()
4790 SDLoc SL(N); in lowerFCMPIntrinsic() local
4793 Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0); in lowerFCMPIntrinsic()
4794 Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1); in lowerFCMPIntrinsic()
4801 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, in lowerFCMPIntrinsic()
4805 return DAG.getZExtOrTrunc(SetCC, SL, VT); in lowerFCMPIntrinsic()
4812 SDLoc SL(N); in lowerBALLOTIntrinsic() local
4816 return DAG.getNode(AMDGPUISD::SETCC, SL, VT, Src.getOperand(0), in lowerBALLOTIntrinsic()
4822 return DAG.getConstant(0, SL, VT); in lowerBALLOTIntrinsic()
4834 return DAG.getCopyFromReg(DAG.getEntryNode(), SL, Exec, VT); in lowerBALLOTIntrinsic()
4841 AMDGPUISD::SETCC, SL, VT, DAG.getZExtOrTrunc(Src, SL, MVT::i32), in lowerBALLOTIntrinsic()
4842 DAG.getConstant(0, SL, MVT::i32), DAG.getCondCode(ISD::SETNE)); in lowerBALLOTIntrinsic()
4865 SDLoc SL(N); in ReplaceNodeResults() local
4866 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_PKRTZ_F16_F32, SL, MVT::i32, in ReplaceNodeResults()
4868 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Cvt)); in ReplaceNodeResults()
4877 SDLoc SL(N); in ReplaceNodeResults() local
4891 Results.push_back(DAG.getNode(Opcode, SL, VT, Src0, Src1)); in ReplaceNodeResults()
4893 SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1); in ReplaceNodeResults()
4894 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, Cvt)); in ReplaceNodeResults()
4918 SDLoc SL(N); in ReplaceNodeResults() local
4921 SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1)); in ReplaceNodeResults()
4922 SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2)); in ReplaceNodeResults()
4926 LHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, LHS); in ReplaceNodeResults()
4927 RHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, RHS); in ReplaceNodeResults()
4931 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, SelectVT, in ReplaceNodeResults()
4935 NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect); in ReplaceNodeResults()
4936 Results.push_back(DAG.getNode(ISD::BITCAST, SL, VT, NewSelect)); in ReplaceNodeResults()
4943 SDLoc SL(N); in ReplaceNodeResults() local
4944 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0)); in ReplaceNodeResults()
4946 SDValue Op = DAG.getNode(ISD::XOR, SL, MVT::i32, in ReplaceNodeResults()
4948 DAG.getConstant(0x80008000, SL, MVT::i32)); in ReplaceNodeResults()
4949 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op)); in ReplaceNodeResults()
4956 SDLoc SL(N); in ReplaceNodeResults() local
4957 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0)); in ReplaceNodeResults()
4959 SDValue Op = DAG.getNode(ISD::AND, SL, MVT::i32, in ReplaceNodeResults()
4961 DAG.getConstant(0x7fff7fff, SL, MVT::i32)); in ReplaceNodeResults()
4962 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op)); in ReplaceNodeResults()
5201 SDLoc SL(Op); in lowerXMULO() local
5212 SDValue ShiftAmt = DAG.getConstant(C.logBase2(), SL, MVT::i32); in lowerXMULO()
5213 SDValue Result = DAG.getNode(ISD::SHL, SL, VT, LHS, ShiftAmt); in lowerXMULO()
5214 SDValue Overflow = DAG.getSetCC(SL, MVT::i1, in lowerXMULO()
5216 SL, VT, Result, ShiftAmt), in lowerXMULO()
5218 return DAG.getMergeValues({ Result, Overflow }, SL); in lowerXMULO()
5222 SDValue Result = DAG.getNode(ISD::MUL, SL, VT, LHS, RHS); in lowerXMULO()
5224 SL, VT, LHS, RHS); in lowerXMULO()
5227 ? DAG.getNode(ISD::SRA, SL, VT, Result, in lowerXMULO()
5228 DAG.getConstant(VT.getScalarSizeInBits() - 1, SL, MVT::i32)) in lowerXMULO()
5229 : DAG.getConstant(0, SL, VT); in lowerXMULO()
5230 SDValue Overflow = DAG.getSetCC(SL, MVT::i1, Top, Sign, ISD::SETNE); in lowerXMULO()
5232 return DAG.getMergeValues({ Result, Overflow }, SL); in lowerXMULO()
5256 SDLoc SL(Op); in lowerTrapEndpgm() local
5258 return DAG.getNode(AMDGPUISD::ENDPGM, SL, MVT::Other, Chain); in lowerTrapEndpgm()
5263 SDLoc SL(Op); in lowerTrapHsaQueuePtr() local
5273 SDValue ToReg = DAG.getCopyToReg(Chain, SL, SGPR01, in lowerTrapHsaQueuePtr()
5279 DAG.getTargetConstant(TrapID, SL, MVT::i16), in lowerTrapHsaQueuePtr()
5283 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops); in lowerTrapHsaQueuePtr()
5288 SDLoc SL(Op); in lowerTrapHsa() local
5294 DAG.getTargetConstant(TrapID, SL, MVT::i16) in lowerTrapHsa()
5296 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops); in lowerTrapHsa()
5300 SDLoc SL(Op); in lowerDEBUGTRAP() local
5318 DAG.getTargetConstant(TrapID, SL, MVT::i16) in lowerDEBUGTRAP()
5320 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops); in lowerDEBUGTRAP()
5372 SDLoc SL(Op); in lowerADDRSPACECAST() local
5376 SDValue FlatNullPtr = DAG.getConstant(0, SL, MVT::i64); in lowerADDRSPACECAST()
5388 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32); in lowerADDRSPACECAST()
5389 SDValue NonNull = DAG.getSetCC(SL, MVT::i1, Src, FlatNullPtr, ISD::SETNE); in lowerADDRSPACECAST()
5390 SDValue Ptr = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src); in lowerADDRSPACECAST()
5392 return DAG.getNode(ISD::SELECT, SL, MVT::i32, in lowerADDRSPACECAST()
5404 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32); in lowerADDRSPACECAST()
5407 = DAG.getSetCC(SL, MVT::i1, Src, SegmentNullPtr, ISD::SETNE); in lowerADDRSPACECAST()
5409 SDValue Aperture = getSegmentAperture(ASC->getSrcAddressSpace(), SL, DAG); in lowerADDRSPACECAST()
5411 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Src, Aperture); in lowerADDRSPACECAST()
5413 return DAG.getNode(ISD::SELECT, SL, MVT::i64, NonNull, in lowerADDRSPACECAST()
5414 DAG.getNode(ISD::BITCAST, SL, MVT::i64, CvtPtr), in lowerADDRSPACECAST()
5421 return DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src); in lowerADDRSPACECAST()
5427 MF.getFunction(), "invalid addrspacecast", SL.getDebugLoc()); in lowerADDRSPACECAST()
5448 SDLoc SL(Op); in lowerINSERT_SUBVECTOR() local
5451 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Ins, in lowerINSERT_SUBVECTOR()
5452 DAG.getConstant(I, SL, MVT::i32)); in lowerINSERT_SUBVECTOR()
5453 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, VecVT, Vec, Elt, in lowerINSERT_SUBVECTOR()
5454 DAG.getConstant(IdxVal + I, SL, MVT::i32)); in lowerINSERT_SUBVECTOR()
5473 SDLoc SL(Op); in lowerINSERT_VECTOR_ELT() local
5477 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Vec); in lowerINSERT_VECTOR_ELT()
5479 SDValue LoHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec, in lowerINSERT_VECTOR_ELT()
5480 DAG.getConstant(0, SL, MVT::i32)); in lowerINSERT_VECTOR_ELT()
5481 SDValue HiHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec, in lowerINSERT_VECTOR_ELT()
5482 DAG.getConstant(1, SL, MVT::i32)); in lowerINSERT_VECTOR_ELT()
5484 SDValue LoVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, LoHalf); in lowerINSERT_VECTOR_ELT()
5485 SDValue HiVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, HiHalf); in lowerINSERT_VECTOR_ELT()
5489 SDValue InsHalf = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, MVT::v2i16, in lowerINSERT_VECTOR_ELT()
5491 DAG.getNode(ISD::BITCAST, SL, MVT::i16, InsVal), in lowerINSERT_VECTOR_ELT()
5492 DAG.getConstant(InsertLo ? Idx : (Idx - 2), SL, MVT::i32)); in lowerINSERT_VECTOR_ELT()
5494 InsHalf = DAG.getNode(ISD::BITCAST, SL, MVT::i32, InsHalf); in lowerINSERT_VECTOR_ELT()
5497 DAG.getBuildVector(MVT::v2i32, SL, { InsHalf, HiHalf }) : in lowerINSERT_VECTOR_ELT()
5498 DAG.getBuildVector(MVT::v2i32, SL, { LoHalf, InsHalf }); in lowerINSERT_VECTOR_ELT()
5500 return DAG.getNode(ISD::BITCAST, SL, VecVT, Concat); in lowerINSERT_VECTOR_ELT()
5513 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT, in lowerINSERT_VECTOR_ELT()
5514 DAG.getSplatBuildVector(VecVT, SL, InsVal)); in lowerINSERT_VECTOR_ELT()
5517 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32); in lowerINSERT_VECTOR_ELT()
5520 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor); in lowerINSERT_VECTOR_ELT()
5522 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec); in lowerINSERT_VECTOR_ELT()
5523 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT, in lowerINSERT_VECTOR_ELT()
5524 DAG.getConstant(0xffff, SL, IntVT), in lowerINSERT_VECTOR_ELT()
5527 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal); in lowerINSERT_VECTOR_ELT()
5528 SDValue RHS = DAG.getNode(ISD::AND, SL, IntVT, in lowerINSERT_VECTOR_ELT()
5529 DAG.getNOT(SL, BFM, IntVT), BCVec); in lowerINSERT_VECTOR_ELT()
5531 SDValue BFI = DAG.getNode(ISD::OR, SL, IntVT, LHS, RHS); in lowerINSERT_VECTOR_ELT()
5532 return DAG.getNode(ISD::BITCAST, SL, VecVT, BFI); in lowerINSERT_VECTOR_ELT()
5537 SDLoc SL(Op); in lowerEXTRACT_VECTOR_ELT() local
5560 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32); in lowerEXTRACT_VECTOR_ELT()
5563 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor); in lowerEXTRACT_VECTOR_ELT()
5565 SDValue BC = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec); in lowerEXTRACT_VECTOR_ELT()
5566 SDValue Elt = DAG.getNode(ISD::SRL, SL, IntVT, BC, ScaledIdx); in lowerEXTRACT_VECTOR_ELT()
5569 SDValue Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Elt); in lowerEXTRACT_VECTOR_ELT()
5570 return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result); in lowerEXTRACT_VECTOR_ELT()
5573 return DAG.getAnyExtOrTrunc(Elt, SL, ResultVT); in lowerEXTRACT_VECTOR_ELT()
5583 SDLoc SL(Op); in lowerVECTOR_SHUFFLE() local
5607 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, in lowerVECTOR_SHUFFLE()
5609 DAG.getConstant(EltIdx, SL, MVT::i32)); in lowerVECTOR_SHUFFLE()
5620 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in lowerVECTOR_SHUFFLE()
5621 Vec0, DAG.getConstant(EltIdx0, SL, MVT::i32)); in lowerVECTOR_SHUFFLE()
5624 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in lowerVECTOR_SHUFFLE()
5625 Vec1, DAG.getConstant(EltIdx1, SL, MVT::i32)); in lowerVECTOR_SHUFFLE()
5626 Pieces.push_back(DAG.getBuildVector(PackVT, SL, { Elt0, Elt1 })); in lowerVECTOR_SHUFFLE()
5630 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces); in lowerVECTOR_SHUFFLE()
5635 SDLoc SL(Op); in lowerBUILD_VECTOR() local
5643 SDValue Lo = DAG.getBuildVector(HalfVT, SL, in lowerBUILD_VECTOR()
5645 SDValue Hi = DAG.getBuildVector(HalfVT, SL, in lowerBUILD_VECTOR()
5648 SDValue CastLo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Lo); in lowerBUILD_VECTOR()
5649 SDValue CastHi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Hi); in lowerBUILD_VECTOR()
5651 SDValue Blend = DAG.getBuildVector(MVT::v2i32, SL, { CastLo, CastHi }); in lowerBUILD_VECTOR()
5652 return DAG.getNode(ISD::BITCAST, SL, VT, Blend); in lowerBUILD_VECTOR()
5663 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo); in lowerBUILD_VECTOR()
5664 SDValue ExtLo = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Lo); in lowerBUILD_VECTOR()
5665 return DAG.getNode(ISD::BITCAST, SL, VT, ExtLo); in lowerBUILD_VECTOR()
5668 Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Hi); in lowerBUILD_VECTOR()
5669 Hi = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Hi); in lowerBUILD_VECTOR()
5671 SDValue ShlHi = DAG.getNode(ISD::SHL, SL, MVT::i32, Hi, in lowerBUILD_VECTOR()
5672 DAG.getConstant(16, SL, MVT::i32)); in lowerBUILD_VECTOR()
5674 return DAG.getNode(ISD::BITCAST, SL, VT, ShlHi); in lowerBUILD_VECTOR()
5676 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo); in lowerBUILD_VECTOR()
5677 Lo = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Lo); in lowerBUILD_VECTOR()
5679 SDValue Or = DAG.getNode(ISD::OR, SL, MVT::i32, Lo, ShlHi); in lowerBUILD_VECTOR()
5680 return DAG.getNode(ISD::BITCAST, SL, VT, Or); in lowerBUILD_VECTOR()
5819 SDLoc SL(Op); in lowerImplicitZextParam() local
5821 DAG, MVT::i32, MVT::i32, SL, DAG.getEntryNode(), Offset, Align(4), false); in lowerImplicitZextParam()
5823 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param, in lowerImplicitZextParam()
6747 SDLoc SL(Op); in LowerINTRINSIC_WO_CHAIN() local
6750 SDValue Aperture = getSegmentAperture(AS, SL, DAG); in LowerINTRINSIC_WO_CHAIN()
6754 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec, in LowerINTRINSIC_WO_CHAIN()
6755 DAG.getConstant(1, SL, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
6756 return DAG.getSetCC(SL, MVT::i1, SrcHi, Aperture, ISD::SETEQ); in LowerINTRINSIC_WO_CHAIN()
7976 const SDLoc &SL, EVT VT) { in getLoadExtOrTrunc() argument
7978 return DAG.getNode(ISD::TRUNCATE, SL, VT, Op); in getLoadExtOrTrunc()
7982 return DAG.getNode(ISD::SIGN_EXTEND, SL, VT, Op); in getLoadExtOrTrunc()
7984 return DAG.getNode(ISD::ZERO_EXTEND, SL, VT, Op); in getLoadExtOrTrunc()
7986 return DAG.getNode(ISD::ANY_EXTEND, SL, VT, Op); in getLoadExtOrTrunc()
8014 SDLoc SL(Ld); in widenLoad() local
8022 MVT::i32, SL, Ld->getChain(), Ptr, in widenLoad()
8039 Cvt = DAG.getNode(ISD::SIGN_EXTEND_INREG, SL, MVT::i32, NewLoad, in widenLoad()
8043 Cvt = DAG.getZeroExtendInReg(NewLoad, SL, TruncVT); in widenLoad()
8055 Cvt = getLoadExtOrTrunc(DAG, Ld->getExtensionType(), Cvt, SL, IntVT); in widenLoad()
8059 Cvt = DAG.getNode(ISD::BITCAST, SL, VT, Cvt); in widenLoad()
8061 return DAG.getMergeValues({ Cvt, NewLoad.getValue(1) }, SL); in widenLoad()
8268 SDLoc SL(Op); in lowerFastUnsafeFDIV() local
8295 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0)); in lowerFastUnsafeFDIV()
8298 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS); in lowerFastUnsafeFDIV()
8304 SDValue FNegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in lowerFastUnsafeFDIV()
8305 return DAG.getNode(AMDGPUISD::RCP, SL, VT, FNegRHS); in lowerFastUnsafeFDIV()
8311 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS); in lowerFastUnsafeFDIV()
8312 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip, Flags); in lowerFastUnsafeFDIV()
8317 SDLoc SL(Op); in lowerFastUnsafeFDIV64() local
8328 SDValue NegY = DAG.getNode(ISD::FNEG, SL, VT, Y); in lowerFastUnsafeFDIV64()
8329 SDValue One = DAG.getConstantFP(1.0, SL, VT); in lowerFastUnsafeFDIV64()
8331 SDValue R = DAG.getNode(AMDGPUISD::RCP, SL, VT, Y); in lowerFastUnsafeFDIV64()
8332 SDValue Tmp0 = DAG.getNode(ISD::FMA, SL, VT, NegY, R, One); in lowerFastUnsafeFDIV64()
8334 R = DAG.getNode(ISD::FMA, SL, VT, Tmp0, R, R); in lowerFastUnsafeFDIV64()
8335 SDValue Tmp1 = DAG.getNode(ISD::FMA, SL, VT, NegY, R, One); in lowerFastUnsafeFDIV64()
8336 R = DAG.getNode(ISD::FMA, SL, VT, Tmp1, R, R); in lowerFastUnsafeFDIV64()
8337 SDValue Ret = DAG.getNode(ISD::FMUL, SL, VT, X, R); in lowerFastUnsafeFDIV64()
8338 SDValue Tmp2 = DAG.getNode(ISD::FMA, SL, VT, NegY, Ret, X); in lowerFastUnsafeFDIV64()
8339 return DAG.getNode(ISD::FMA, SL, VT, Tmp2, R, Ret); in lowerFastUnsafeFDIV64()
8342 static SDValue getFPBinOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL, in getFPBinOp() argument
8346 return DAG.getNode(Opcode, SL, VT, A, B, Flags); in getFPBinOp()
8359 return DAG.getNode(Opcode, SL, VTList, in getFPBinOp()
8364 static SDValue getFPTernOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL, in getFPTernOp() argument
8368 return DAG.getNode(Opcode, SL, VT, {A, B, C}, Flags); in getFPTernOp()
8381 return DAG.getNode(Opcode, SL, VTList, in getFPTernOp()
8390 SDLoc SL(Op); in LowerFDIV16() local
8394 SDValue CvtSrc0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0); in LowerFDIV16()
8395 SDValue CvtSrc1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1); in LowerFDIV16()
8397 SDValue RcpSrc1 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, CvtSrc1); in LowerFDIV16()
8398 SDValue Quot = DAG.getNode(ISD::FMUL, SL, MVT::f32, CvtSrc0, RcpSrc1); in LowerFDIV16()
8400 SDValue FPRoundFlag = DAG.getTargetConstant(0, SL, MVT::i32); in LowerFDIV16()
8401 SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag); in LowerFDIV16()
8403 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f16, BestQuot, Src1, Src0); in LowerFDIV16()
8408 SDLoc SL(Op); in lowerFDIV_FAST() local
8412 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS); in lowerFDIV_FAST()
8415 const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32); in lowerFDIV_FAST()
8418 const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32); in lowerFDIV_FAST()
8420 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32); in lowerFDIV_FAST()
8425 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT); in lowerFDIV_FAST()
8427 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One); in lowerFDIV_FAST()
8430 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3); in lowerFDIV_FAST()
8433 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1); in lowerFDIV_FAST()
8435 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0); in lowerFDIV_FAST()
8437 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul); in lowerFDIV_FAST()
8443 const SDLoc &SL, const GCNSubtarget *ST) { in getSPDenormModeValue() argument
8450 return DAG.getTargetConstant(Mode, SL, MVT::i32); in getSPDenormModeValue()
8464 SDLoc SL(Op); in LowerFDIV32() local
8468 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32); in LowerFDIV32()
8472 SDValue DenominatorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, in LowerFDIV32()
8474 SDValue NumeratorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, in LowerFDIV32()
8478 SDValue ApproxRcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, in LowerFDIV32()
8480 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32, in LowerFDIV32()
8486 const SDValue BitField = DAG.getTargetConstant(Denorm32Reg, SL, MVT::i32); in LowerFDIV32()
8500 getSPDenormModeValue(FP_DENORM_FLUSH_NONE, DAG, SL, Subtarget); in LowerFDIV32()
8502 EnableDenorm = DAG.getNode(AMDGPUISD::DENORM_MODE, SL, BindParamVTs, in LowerFDIV32()
8506 SL, MVT::i32); in LowerFDIV32()
8508 DAG.getMachineNode(AMDGPU::S_SETREG_B32, SL, BindParamVTs, in LowerFDIV32()
8518 NegDivScale0 = DAG.getMergeValues(Ops, SL); in LowerFDIV32()
8521 SDValue Fma0 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, in LowerFDIV32()
8524 SDValue Fma1 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp, in LowerFDIV32()
8527 SDValue Mul = getFPBinOp(DAG, ISD::FMUL, SL, MVT::f32, NumeratorScaled, in LowerFDIV32()
8530 SDValue Fma2 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Mul, in LowerFDIV32()
8533 SDValue Fma3 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, in LowerFDIV32()
8536 SDValue Fma4 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Fma3, in LowerFDIV32()
8543 getSPDenormModeValue(FP_DENORM_FLUSH_IN_FLUSH_OUT, DAG, SL, Subtarget); in LowerFDIV32()
8545 DisableDenorm = DAG.getNode(AMDGPUISD::DENORM_MODE, SL, MVT::Other, in LowerFDIV32()
8550 DAG.getConstant(FP_DENORM_FLUSH_IN_FLUSH_OUT, SL, MVT::i32); in LowerFDIV32()
8553 AMDGPU::S_SETREG_B32, SL, MVT::Other, in LowerFDIV32()
8557 SDValue OutputChain = DAG.getNode(ISD::TokenFactor, SL, MVT::Other, in LowerFDIV32()
8563 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f32, in LowerFDIV32()
8566 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f32, Fmas, RHS, LHS, Flags); in LowerFDIV32()
8573 SDLoc SL(Op); in LowerFDIV64() local
8577 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64); in LowerFDIV64()
8581 SDValue DivScale0 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, Y, Y, X); in LowerFDIV64()
8583 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0); in LowerFDIV64()
8585 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0); in LowerFDIV64()
8587 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One); in LowerFDIV64()
8589 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp); in LowerFDIV64()
8591 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One); in LowerFDIV64()
8593 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X); in LowerFDIV64()
8595 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1); in LowerFDIV64()
8596 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64()
8598 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64, in LowerFDIV64()
8607 const SDValue Hi = DAG.getConstant(1, SL, MVT::i32); in LowerFDIV64()
8610 SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X); in LowerFDIV64()
8611 SDValue DenBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Y); in LowerFDIV64()
8612 SDValue Scale0BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale0); in LowerFDIV64()
8613 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1); in LowerFDIV64()
8615 SDValue NumHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, NumBC, Hi); in LowerFDIV64()
8616 SDValue DenHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, DenBC, Hi); in LowerFDIV64()
8619 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale0BC, Hi); in LowerFDIV64()
8621 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale1BC, Hi); in LowerFDIV64()
8623 SDValue CmpDen = DAG.getSetCC(SL, MVT::i1, DenHi, Scale0Hi, ISD::SETEQ); in LowerFDIV64()
8624 SDValue CmpNum = DAG.getSetCC(SL, MVT::i1, NumHi, Scale1Hi, ISD::SETEQ); in LowerFDIV64()
8625 Scale = DAG.getNode(ISD::XOR, SL, MVT::i1, CmpNum, CmpDen); in LowerFDIV64()
8630 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f64, in LowerFDIV64()
8633 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f64, Fmas, Y, X); in LowerFDIV64()
8888 SDLoc SL(N); in performSHLPtrCombine() local
8891 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1); in performSHLPtrCombine()
8892 SDValue COffset = DAG.getConstant(Offset, SL, VT); in performSHLPtrCombine()
8899 return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset, Flags); in performSHLPtrCombine()
8919 SDLoc SL(N); in performMemSDNodeCombine() local
8952 const SDLoc &SL, in splitBinaryBitConstantOp() argument
8966 return splitBinaryBitConstantOpImpl(DCI, SL, Opc, LHS, ValLo, ValHi); in splitBinaryBitConstantOp()
9088 SDLoc SL(N); in performAndCombine() local
9089 SDValue BFE = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32, in performAndCombine()
9091 DAG.getConstant(Offset, SL, MVT::i32), in performAndCombine()
9092 DAG.getConstant(Bits, SL, MVT::i32)); in performAndCombine()
9094 SDValue Ext = DAG.getNode(ISD::AssertZext, SL, VT, BFE, in performAndCombine()
9344 SDLoc SL(N); in performOrCombine() local
9347 SDValue LowOr = DAG.getNode(ISD::OR, SL, MVT::i32, LowLHS, ExtSrc); in performOrCombine()
9352 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in performOrCombine()
9354 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec); in performOrCombine()
9682 SelectionDAG &DAG, const SDLoc &SL, EVT VT, const APFloat &C) const { in getCanonicalConstantFP() argument
9685 return DAG.getConstantFP(0.0, SL, VT); in getCanonicalConstantFP()
9692 return DAG.getConstantFP(CanonicalQNaN, SL, VT); in getCanonicalConstantFP()
9700 return DAG.getConstantFP(CanonicalQNaN, SL, VT); in getCanonicalConstantFP()
9704 return DAG.getConstantFP(C, SL, VT); in getCanonicalConstantFP()
9738 SDLoc SL(N); in performFCanonicalizeCombine() local
9748 NewElts[I] = getCanonicalConstantFP(DAG, SL, EltVT, in performFCanonicalizeCombine()
9754 NewElts[I] = DAG.getNode(ISD::FCANONICALIZE, SL, EltVT, Op); in performFCanonicalizeCombine()
9764 NewElts[1]: DAG.getConstantFP(0.0f, SL, EltVT); in performFCanonicalizeCombine()
9769 NewElts[0] : DAG.getConstantFP(0.0f, SL, EltVT); in performFCanonicalizeCombine()
9772 return DAG.getBuildVector(VT, SL, NewElts); in performFCanonicalizeCombine()
9786 SDLoc SL(N); in performFCanonicalizeCombine() local
9787 SDValue Canon0 = DAG.getNode(ISD::FCANONICALIZE, SL, VT, in performFCanonicalizeCombine()
9789 SDValue Canon1 = getCanonicalConstantFP(DAG, SL, VT, CRHS->getValueAPF()); in performFCanonicalizeCombine()
9792 return DAG.getNode(N0.getOpcode(), SL, VT, Canon0, Canon1); in performFCanonicalizeCombine()
9821 SelectionDAG &DAG, const SDLoc &SL, in performIntMed3ImmCombine() argument
9842 return DAG.getNode(Med3Opc, SL, VT, in performIntMed3ImmCombine()
9851 SDValue Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0)); in performIntMed3ImmCombine()
9852 SDValue Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1)); in performIntMed3ImmCombine()
9853 SDValue Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1); in performIntMed3ImmCombine()
9855 SDValue Med3 = DAG.getNode(Med3Opc, SL, NVT, Tmp1, Tmp2, Tmp3); in performIntMed3ImmCombine()
9856 return DAG.getNode(ISD::TRUNCATE, SL, VT, Med3); in performIntMed3ImmCombine()
9875 const SDLoc &SL, in performFPMed3ImmCombine() argument
9900 return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Op0.getOperand(0)); in performFPMed3ImmCombine()
9919 return DAG.getNode(AMDGPUISD::FMED3, SL, K0->getValueType(0), in performFPMed3ImmCombine()
10016 SDLoc SL(N); in performFMed3Combine() local
10026 return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Src2); in performFMed3Combine()
10047 return DAG.getNode(AMDGPUISD::CLAMP, SL, VT, Src0); in performFMed3Combine()
10116 SDLoc SL(N); in performExtractVectorEltCombine() local
10119 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in performExtractVectorEltCombine()
10121 return DAG.getNode(Vec.getOpcode(), SL, EltVT, Elt); in performExtractVectorEltCombine()
10130 SDLoc SL(N); in performExtractVectorEltCombine() local
10151 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in performExtractVectorEltCombine()
10153 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in performExtractVectorEltCombine()
10158 return DAG.getNode(Opc, SL, EltVT, Elt0, Elt1, Vec->getFlags()); in performExtractVectorEltCombine()
10168 SDLoc SL(N); in performExtractVectorEltCombine() local
10172 SDValue IC = DAG.getVectorIdxConstant(I, SL); in performExtractVectorEltCombine()
10173 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Vec, IC); in performExtractVectorEltCombine()
10177 V = DAG.getSelectCC(SL, Idx, IC, Elt, V, ISD::SETEQ); in performExtractVectorEltCombine()
10200 SDLoc SL(N); in performExtractVectorEltCombine() local
10202 SDValue Cast = DAG.getNode(ISD::BITCAST, SL, NewVT, Vec); in performExtractVectorEltCombine()
10205 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Cast, in performExtractVectorEltCombine()
10206 DAG.getConstant(EltIdx, SL, MVT::i32)); in performExtractVectorEltCombine()
10208 SDValue Srl = DAG.getNode(ISD::SRL, SL, MVT::i32, Elt, in performExtractVectorEltCombine()
10209 DAG.getConstant(LeftoverBitIdx, SL, MVT::i32)); in performExtractVectorEltCombine()
10212 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, EltVT.changeTypeToInteger(), Srl); in performExtractVectorEltCombine()
10214 return DAG.getNode(ISD::BITCAST, SL, EltVT, Trunc); in performExtractVectorEltCombine()
10234 SDLoc SL(N); in performInsertVectorEltCombine() local
10240 SDValue IC = DAG.getConstant(I, SL, IdxVT); in performInsertVectorEltCombine()
10241 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Vec, IC); in performInsertVectorEltCombine()
10242 SDValue V = DAG.getSelectCC(SL, Idx, IC, Ins, Elt, ISD::SETEQ); in performInsertVectorEltCombine()
10246 return DAG.getBuildVector(VecVT, SL, Ops); in performInsertVectorEltCombine()
10308 SDLoc SL(N); in reassociateScalarOps() local
10309 SDValue Add1 = DAG.getNode(Opc, SL, VT, Op0, Op1); in reassociateScalarOps()
10310 return DAG.getNode(Opc, SL, VT, Add1, Op2); in reassociateScalarOps()
10313 static SDValue getMad64_32(SelectionDAG &DAG, const SDLoc &SL, in getMad64_32() argument
10319 SDValue Mad = DAG.getNode(MadOpc, SL, VTs, N0, N1, N2); in getMad64_32()
10320 return DAG.getNode(ISD::TRUNCATE, SL, VT, Mad); in getMad64_32()
10327 SDLoc SL(N); in performAddCombine() local
10345 MulLHS = DAG.getZExtOrTrunc(MulLHS, SL, MVT::i32); in performAddCombine()
10346 MulRHS = DAG.getZExtOrTrunc(MulRHS, SL, MVT::i32); in performAddCombine()
10347 AddRHS = DAG.getZExtOrTrunc(AddRHS, SL, MVT::i64); in performAddCombine()
10348 return getMad64_32(DAG, SL, VT, MulLHS, MulRHS, AddRHS, false); in performAddCombine()
10352 MulLHS = DAG.getSExtOrTrunc(MulLHS, SL, MVT::i32); in performAddCombine()
10353 MulRHS = DAG.getSExtOrTrunc(MulRHS, SL, MVT::i32); in performAddCombine()
10354 AddRHS = DAG.getSExtOrTrunc(AddRHS, SL, MVT::i64); in performAddCombine()
10355 return getMad64_32(DAG, SL, VT, MulLHS, MulRHS, AddRHS, true); in performAddCombine()
10387 SDValue Args[] = { LHS, DAG.getConstant(0, SL, MVT::i32), Cond }; in performAddCombine()
10389 return DAG.getNode(Opc, SL, VTList, Args); in performAddCombine()
10410 SDLoc SL(N); in performSubCombine() local
10428 SDValue Args[] = { LHS, DAG.getConstant(0, SL, MVT::i32), Cond }; in performSubCombine()
10430 return DAG.getNode(Opc, SL, VTList, Args); in performSubCombine()
10478 SDLoc SL(N); in performFAddCombine() local
10491 const SDValue Two = DAG.getConstantFP(2.0, SL, VT); in performFAddCombine()
10492 return DAG.getNode(FusedOp, SL, VT, A, Two, RHS); in performFAddCombine()
10503 const SDValue Two = DAG.getConstantFP(2.0, SL, VT); in performFAddCombine()
10504 return DAG.getNode(FusedOp, SL, VT, A, Two, LHS); in performFAddCombine()
10518 SDLoc SL(N); in performFSubCombine() local
10535 const SDValue Two = DAG.getConstantFP(2.0, SL, VT); in performFSubCombine()
10536 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFSubCombine()
10538 return DAG.getNode(FusedOp, SL, VT, A, Two, NegRHS); in performFSubCombine()
10550 const SDValue NegTwo = DAG.getConstantFP(-2.0, SL, VT); in performFSubCombine()
10551 return DAG.getNode(FusedOp, SL, VT, A, NegTwo, LHS); in performFSubCombine()
10563 SDLoc SL(N); in performFMACombine() local
10627 return DAG.getNode(AMDGPUISD::FDOT2, SL, MVT::f32, Vec1, Vec2, FMAAcc, in performFMACombine()
10628 DAG.getTargetConstant(0, SL, MVT::i1)); in performFMACombine()
10637 SDLoc SL(N); in performSetCCCombine() local
10664 return DAG.getNode(ISD::XOR, SL, MVT::i1, LHS.getOperand(0), in performSetCCCombine()
10665 DAG.getConstant(-1, SL, MVT::i1)); in performSetCCCombine()
10690 return DAG.getNode(ISD::XOR, SL, MVT::i1, LHS.getOperand(0), in performSetCCCombine()
10691 DAG.getConstant(-1, SL, MVT::i1)); in performSetCCCombine()
10722 return DAG.getNode(AMDGPUISD::FP_CLASS, SL, MVT::i1, LHS.getOperand(0), in performSetCCCombine()
10723 DAG.getConstant(Mask, SL, MVT::i32)); in performSetCCCombine()
10733 SDLoc SL(N); in performCvtF32UByteNCombine() local
10760 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0 + ShiftOffset / 8, SL, in performCvtF32UByteNCombine()
10779 return DAG.getNode(N->getOpcode(), SL, MVT::f32, DemandedSrc); in performCvtF32UByteNCombine()
10885 SDLoc SL(N); in PerformDAGCombine() local
10889 Src = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Src); in PerformDAGCombine()
10891 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Src); in PerformDAGCombine()
10892 return DAG.getNode(ISD::BITCAST, SL, VT, Ext); in PerformDAGCombine()
11114 SDLoc SL(Node); in legalizeTargetIndependentNode() local
11121 = DAG.getCopyToReg(Node->getOperand(0), SL, VReg, SrcVal, in legalizeTargetIndependentNode()
11124 = DAG.getCopyToReg(ToVReg, SL, SDValue(DestReg, 0), in legalizeTargetIndependentNode()