Lines Matching refs:Ld
7994 SDValue SITargetLowering::widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const { in widenLoad() argument
7996 if (Ld->getAlignment() < 4 || Ld->isDivergent()) in widenLoad()
8000 unsigned AS = Ld->getAddressSpace(); in widenLoad()
8003 (AS != AMDGPUAS::GLOBAL_ADDRESS || !Ld->isInvariant())) in widenLoad()
8009 EVT MemVT = Ld->getMemoryVT(); in widenLoad()
8014 SDLoc SL(Ld); in widenLoad()
8016 assert((!MemVT.isVector() || Ld->getExtensionType() == ISD::NON_EXTLOAD) && in widenLoad()
8020 SDValue Ptr = Ld->getBasePtr(); in widenLoad()
8022 MVT::i32, SL, Ld->getChain(), Ptr, in widenLoad()
8023 Ld->getOffset(), in widenLoad()
8024 Ld->getPointerInfo(), MVT::i32, in widenLoad()
8025 Ld->getAlignment(), in widenLoad()
8026 Ld->getMemOperand()->getFlags(), in widenLoad()
8027 Ld->getAAInfo(), in widenLoad()
8032 assert(Ld->getExtensionType() == ISD::NON_EXTLOAD && in widenLoad()
8038 if (Ld->getExtensionType() == ISD::SEXTLOAD) { in widenLoad()
8041 } else if (Ld->getExtensionType() == ISD::ZEXTLOAD || in widenLoad()
8042 Ld->getExtensionType() == ISD::NON_EXTLOAD) { in widenLoad()
8045 assert(Ld->getExtensionType() == ISD::EXTLOAD); in widenLoad()
8048 EVT VT = Ld->getValueType(0); in widenLoad()
8055 Cvt = getLoadExtOrTrunc(DAG, Ld->getExtensionType(), Cvt, SL, IntVT); in widenLoad()