1083         const AMDGPU::ImageDimIntrinsicInfo *Intr  in getTgtMemIntrinsic()  local
1086           AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);  in getTgtMemIntrinsic()
4986 unsigned SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {  in isCFIntrinsic()
4987   if (Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN) {  in isCFIntrinsic()
4988     switch (cast<ConstantSDNode>(Intr->getOperand(1))->getZExtValue()) {  in isCFIntrinsic()
5041   SDNode *Intr = BRCOND.getOperand(1).getNode();  in LowerBRCOND()  local
5046   if (Intr->getOpcode() == ISD::SETCC) {  in LowerBRCOND()
5048     SetCC = Intr;  in LowerBRCOND()
5049     Intr = SetCC->getOperand(0).getNode();  in LowerBRCOND()
5058   unsigned CFNode = isCFIntrinsic(Intr);  in LowerBRCOND()
5064   bool HaveChain = Intr->getOpcode() == ISD::INTRINSIC_VOID ||  in LowerBRCOND()
5065                    Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN;  in LowerBRCOND()
5077   Ops.append(Intr->op_begin() + (HaveChain ?  2 : 1), Intr->op_end());  in LowerBRCOND()
5080   ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());  in LowerBRCOND()
5107   for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {  in LowerBRCOND()
5108     SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);  in LowerBRCOND()
5123     SDValue(Intr, Intr->getNumValues() - 1),  in LowerBRCOND()
5124     Intr->getOperand(0));  in LowerBRCOND()
6013                                      const AMDGPU::ImageDimIntrinsicInfo *Intr,  in lowerImage()  argument
6019       AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);  in lowerImage()
6020   const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfo(Intr->Dim);  in lowerImage()
6022       AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode);  in lowerImage()
6024       AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode);  in lowerImage()
6025   unsigned IntrOpcode = Intr->BaseOpcode;  in lowerImage()
6063         cast<ConstantSDNode>(Op.getOperand(ArgOffset + Intr->DMaskIndex));  in lowerImage()
6109   unsigned VAddrEnd = ArgOffset + Intr->VAddrEnd;  in lowerImage()
6115             Op.getOperand(ArgOffset + Intr->LodIndex))) {  in lowerImage()
6126             Op.getOperand(ArgOffset + Intr->MipIndex))) {  in lowerImage()
6135   for (unsigned I = Intr->VAddrStart; I < Intr->GradientStart; I++)  in lowerImage()
6140       Op.getOperand(ArgOffset + Intr->GradientStart).getSimpleValueType();  in lowerImage()
6145   VAddrVT = Op.getOperand(ArgOffset + Intr->CoordStart).getSimpleValueType();  in lowerImage()
6175         AMDGPU::getMIMGG16MappingInfo(Intr->BaseOpcode);  in lowerImage()
6184                               ArgOffset + Intr->GradientStart,  in lowerImage()
6185                               ArgOffset + Intr->CoordStart, Intr->NumGradients);  in lowerImage()
6187     for (unsigned I = ArgOffset + Intr->GradientStart;  in lowerImage()
6188          I < ArgOffset + Intr->CoordStart; I++)  in lowerImage()
6195                               ArgOffset + Intr->CoordStart, VAddrEnd,  in lowerImage()
6199     for (unsigned I = ArgOffset + Intr->CoordStart; I < VAddrEnd; I++)  in lowerImage()
6228         cast<ConstantSDNode>(Op.getOperand(ArgOffset + Intr->UnormIndex));  in lowerImage()
6235   SDValue TexFail = Op.getOperand(ArgOffset + Intr->TexFailCtrlIndex);  in lowerImage()
6278       Op.getOperand(ArgOffset + Intr->CachePolicyIndex))->getZExtValue();  in lowerImage()
6291   Ops.push_back(Op.getOperand(ArgOffset + Intr->RsrcIndex));  in lowerImage()
6293     Ops.push_back(Op.getOperand(ArgOffset + Intr->SampIndex));  in lowerImage()