350   Register ScratchRsrcReg = MFI->getScratchRSrcReg();  in getEntryFunctionReservedScratchRsrcReg()  local
352   if (!ScratchRsrcReg || (!MRI.isPhysRegUsed(ScratchRsrcReg) &&  in getEntryFunctionReservedScratchRsrcReg()
357       ScratchRsrcReg != TRI->reservedPrivateSegmentBufferReg(MF))  in getEntryFunctionReservedScratchRsrcReg()
358     return ScratchRsrcReg;  in getEntryFunctionReservedScratchRsrcReg()
382       MRI.replaceRegWith(ScratchRsrcReg, Reg);  in getEntryFunctionReservedScratchRsrcReg()
388   return ScratchRsrcReg;  in getEntryFunctionReservedScratchRsrcReg()
432   Register ScratchRsrcReg;  in emitEntryFunctionPrologue()  local
434     ScratchRsrcReg = getEntryFunctionReservedScratchRsrcReg(MF);  in emitEntryFunctionPrologue()
437   if (ScratchRsrcReg) {  in emitEntryFunctionPrologue()
440         OtherBB.addLiveIn(ScratchRsrcReg);  in emitEntryFunctionPrologue()
451     if (ScratchRsrcReg && PreloadedScratchRsrcReg) {  in emitEntryFunctionPrologue()
470   if (TRI->isSubRegisterEq(ScratchRsrcReg, PreloadedScratchWaveOffsetReg)) {  in emitEntryFunctionPrologue()
478           !TRI->isSubRegisterEq(ScratchRsrcReg, Reg) && GITPtrLoReg != Reg) {  in emitEntryFunctionPrologue()
508   if ((NeedsFlatScratchInit || ScratchRsrcReg) &&  in emitEntryFunctionPrologue()
518   if (ScratchRsrcReg) {  in emitEntryFunctionPrologue()
521                                          ScratchRsrcReg, ScratchWaveOffsetReg);  in emitEntryFunctionPrologue()
529     Register ScratchRsrcReg, Register ScratchWaveOffsetReg) const {  in emitEntryFunctionScratchRsrcRegSetup()  argument
540     Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);  in emitEntryFunctionScratchRsrcRegSetup()
541     Register Rsrc03 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);  in emitEntryFunctionScratchRsrcRegSetup()
557     BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg)  in emitEntryFunctionScratchRsrcRegSetup()
561       .addReg(ScratchRsrcReg, RegState::ImplicitDefine)  in emitEntryFunctionScratchRsrcRegSetup()
581     Register Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);  in emitEntryFunctionScratchRsrcRegSetup()
582     Register Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);  in emitEntryFunctionScratchRsrcRegSetup()
588       Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);  in emitEntryFunctionScratchRsrcRegSetup()
595           .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
610           .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
616       Register Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);  in emitEntryFunctionScratchRsrcRegSetup()
617       Register Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);  in emitEntryFunctionScratchRsrcRegSetup()
621         .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
625         .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
631       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
635       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
639     if (ScratchRsrcReg != PreloadedScratchRsrcReg) {  in emitEntryFunctionScratchRsrcRegSetup()
640       BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)  in emitEntryFunctionScratchRsrcRegSetup()
654   Register ScratchRsrcSub0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);  in emitEntryFunctionScratchRsrcRegSetup()
655   Register ScratchRsrcSub1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);  in emitEntryFunctionScratchRsrcRegSetup()
662       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()
666       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);  in emitEntryFunctionScratchRsrcRegSetup()